/** \file hdr_rcc.h
 * \brief Header with definition of bits in RCC control registers
 * \author Freddie Chopin, http://www.freddiechopin.info/
 * \date 2012-03-22
 */

/******************************************************************************
* chip: STM32F4x
* compiler: arm-none-eabi-gcc (GNU Tools for ARM Embedded Processors) 4.6.2
* 	20110921 (release) [ARM/embedded-4_6-branch revision 182083]
******************************************************************************/

#ifndef HDR_RCC_H_
#define HDR_RCC_H_

#include "hdr/hdr_bitband.h"

/*
+=============================================================================+
| global definitions
+=============================================================================+
*/

/*
+-----------------------------------------------------------------------------+
| RCC_CR - Clock Control Register
+-----------------------------------------------------------------------------+
*/

#define RCC_CR_PLLI2SRDY_bit				27
#define RCC_CR_PLLI2SON_bit					26
#define RCC_CR_PLLRDY_bit					25
#define RCC_CR_PLLON_bit					24
#define RCC_CR_CSSON_bit					19
#define RCC_CR_HSEBYP_bit					18
#define RCC_CR_HSERDY_bit					17
#define RCC_CR_HSEON_bit					16

#define RCC_CR_HSICAL_bit					8
#define RCC_CR_HSICAL_0_bit					8
#define RCC_CR_HSICAL_1_bit					9
#define RCC_CR_HSICAL_2_bit					10
#define RCC_CR_HSICAL_3_bit					11
#define RCC_CR_HSICAL_4_bit					12
#define RCC_CR_HSICAL_5_bit					13
#define RCC_CR_HSICAL_6_bit					14
#define RCC_CR_HSICAL_7_bit					15

#define RCC_CR_HSITRIM_bit					3
#define RCC_CR_HSITRIM_0_bit				3
#define RCC_CR_HSITRIM_1_bit				4
#define RCC_CR_HSITRIM_2_bit				5
#define RCC_CR_HSITRIM_3_bit				6
#define RCC_CR_HSITRIM_4_bit				7

#define RCC_CR_HSIRDY_bit					1
#define RCC_CR_HSION_bit					0

#define RCC_CR_PLLI2SRDY_bb					bitband_t m_BITBAND_PERIPH(&RCC->CR,RCC_CR_PLLI2SRDY_bit)
#define RCC_CR_PLLI2SON_bb					bitband_t m_BITBAND_PERIPH(&RCC->CR,RCC_CR_PLLI2SON_bit)
#define RCC_CR_PLLRDY_bb					bitband_t m_BITBAND_PERIPH(&RCC->CR, RCC_CR_PLLRDY_bit)
#define RCC_CR_PLLON_bb						bitband_t m_BITBAND_PERIPH(&RCC->CR, RCC_CR_PLLON_bit)
#define RCC_CR_CSSON_bb						bitband_t m_BITBAND_PERIPH(&RCC->CR, RCC_CR_CSSON_bit)
#define RCC_CR_HSEBYP_bb					bitband_t m_BITBAND_PERIPH(&RCC->CR, RCC_CR_HSEBYP_bit)
#define RCC_CR_HSERDY_bb					bitband_t m_BITBAND_PERIPH(&RCC->CR, RCC_CR_HSERDY_bit)
#define RCC_CR_HSEON_bb						bitband_t m_BITBAND_PERIPH(&RCC->CR, RCC_CR_HSEON_bit)

#define RCC_CR_HSICAL_0_bb					bitband_t m_BITBAND_PERIPH(&RCC->CR, RCC_CR_HSICAL_0_bit)
#define RCC_CR_HSICAL_1_bb					bitband_t m_BITBAND_PERIPH(&RCC->CR, RCC_CR_HSICAL_1_bit)
#define RCC_CR_HSICAL_2_bb					bitband_t m_BITBAND_PERIPH(&RCC->CR, RCC_CR_HSICAL_2_bit)
#define RCC_CR_HSICAL_3_bb					bitband_t m_BITBAND_PERIPH(&RCC->CR, RCC_CR_HSICAL_3_bit)
#define RCC_CR_HSICAL_4_bb					bitband_t m_BITBAND_PERIPH(&RCC->CR, RCC_CR_HSICAL_4_bit)
#define RCC_CR_HSICAL_5_bb					bitband_t m_BITBAND_PERIPH(&RCC->CR, RCC_CR_HSICAL_5_bit)
#define RCC_CR_HSICAL_6_bb					bitband_t m_BITBAND_PERIPH(&RCC->CR, RCC_CR_HSICAL_6_bit)
#define RCC_CR_HSICAL_7_bb					bitband_t m_BITBAND_PERIPH(&RCC->CR, RCC_CR_HSICAL_7_bit)

#define RCC_CR_HSITRIM_0_bb					bitband_t m_BITBAND_PERIPH(&RCC->CR, RCC_CR_HSITRIM_0_bit)
#define RCC_CR_HSITRIM_1_bb					bitband_t m_BITBAND_PERIPH(&RCC->CR, RCC_CR_HSITRIM_1_bit)
#define RCC_CR_HSITRIM_2_bb					bitband_t m_BITBAND_PERIPH(&RCC->CR, RCC_CR_HSITRIM_2_bit)
#define RCC_CR_HSITRIM_3_bb					bitband_t m_BITBAND_PERIPH(&RCC->CR, RCC_CR_HSITRIM_3_bit)
#define RCC_CR_HSITRIM_4_bb					bitband_t m_BITBAND_PERIPH(&RCC->CR, RCC_CR_HSITRIM_4_bit)

#define RCC_CR_HSIRDY_bb					bitband_t m_BITBAND_PERIPH(&RCC->CR, RCC_CR_HSIRDY_bit)
#define RCC_CR_HSION_bb						bitband_t m_BITBAND_PERIPH(&RCC->CR, RCC_CR_HSION_bit)

/*
+-----------------------------------------------------------------------------+
| RCC_PLLCFGR - RCC PLL configuration register
+-----------------------------------------------------------------------------+
*/

#define RCC_PLLCFGR_PLLQ_bit				24
#define RCC_PLLCFGR_PLLQ_0_bit				24
#define RCC_PLLCFGR_PLLQ_1_bit				25
#define RCC_PLLCFGR_PLLQ_2_bit				26
#define RCC_PLLCFGR_PLLQ_3_bit				27

#define RCC_PLLCFGR_PLLSRC_bit				22

#define RCC_PLLCFGR_PLLP_bit				16
#define RCC_PLLCFGR_PLLP_0_bit				16
#define RCC_PLLCFGR_PLLP_1_bit				17

#define RCC_PLLCFGR_PLLN_bit				6
#define RCC_PLLCFGR_PLLN_0_bit				6
#define RCC_PLLCFGR_PLLN_1_bit				7
#define RCC_PLLCFGR_PLLN_2_bit				8
#define RCC_PLLCFGR_PLLN_3_bit				9
#define RCC_PLLCFGR_PLLN_4_bit				10
#define RCC_PLLCFGR_PLLN_5_bit				11
#define RCC_PLLCFGR_PLLN_6_bit				12
#define RCC_PLLCFGR_PLLN_7_bit				13
#define RCC_PLLCFGR_PLLN_8_bit				14

#define RCC_PLLCFGR_PLLM_bit				0
#define RCC_PLLCFGR_PLLM_0_bit				0
#define RCC_PLLCFGR_PLLM_1_bit				1
#define RCC_PLLCFGR_PLLM_2_bit				2
#define RCC_PLLCFGR_PLLM_3_bit				3
#define RCC_PLLCFGR_PLLM_4_bit				4
#define RCC_PLLCFGR_PLLM_5_bit				5

#define RCC_PLLCFGR_PLLQ_DIV2_value			2
#define RCC_PLLCFGR_PLLQ_DIV3_value			3
#define RCC_PLLCFGR_PLLQ_DIV4_value			4
#define RCC_PLLCFGR_PLLQ_DIV5_value			5
#define RCC_PLLCFGR_PLLQ_DIV6_value			6
#define RCC_PLLCFGR_PLLQ_DIV7_value			7
#define RCC_PLLCFGR_PLLQ_DIV8_value			8
#define RCC_PLLCFGR_PLLQ_DIV9_value			9
#define RCC_PLLCFGR_PLLQ_DIV10_value		10
#define RCC_PLLCFGR_PLLQ_DIV11_value		11
#define RCC_PLLCFGR_PLLQ_DIV12_value		12
#define RCC_PLLCFGR_PLLQ_DIV13_value		13
#define RCC_PLLCFGR_PLLQ_DIV14_value		14
#define RCC_PLLCFGR_PLLQ_DIV15_value		15
#define RCC_PLLCFGR_PLLQ_mask				15

#define RCC_PLLCFGR_PLLP_DIV2_value			0
#define RCC_PLLCFGR_PLLP_DIV4_value			1
#define RCC_PLLCFGR_PLLP_DIV6_value			2
#define RCC_PLLCFGR_PLLP_DIV8_value			3
#define RCC_PLLCFGR_PLLP_mask				3

#define RCC_PLLCFGR_PLLN_MUL64_value		64
#define RCC_PLLCFGR_PLLN_MUL65_value		65
#define RCC_PLLCFGR_PLLN_MUL66_value		66
#define RCC_PLLCFGR_PLLN_MUL67_value		67
#define RCC_PLLCFGR_PLLN_MUL68_value		68
#define RCC_PLLCFGR_PLLN_MUL69_value		69
#define RCC_PLLCFGR_PLLN_MUL70_value		70
#define RCC_PLLCFGR_PLLN_MUL71_value		71
#define RCC_PLLCFGR_PLLN_MUL72_value		72
#define RCC_PLLCFGR_PLLN_MUL73_value		73
#define RCC_PLLCFGR_PLLN_MUL74_value		74
#define RCC_PLLCFGR_PLLN_MUL75_value		75
#define RCC_PLLCFGR_PLLN_MUL76_value		76
#define RCC_PLLCFGR_PLLN_MUL77_value		77
#define RCC_PLLCFGR_PLLN_MUL78_value		78
#define RCC_PLLCFGR_PLLN_MUL79_value		79
#define RCC_PLLCFGR_PLLN_MUL80_value		80
#define RCC_PLLCFGR_PLLN_MUL81_value		81
#define RCC_PLLCFGR_PLLN_MUL82_value		82
#define RCC_PLLCFGR_PLLN_MUL83_value		83
#define RCC_PLLCFGR_PLLN_MUL84_value		84
#define RCC_PLLCFGR_PLLN_MUL85_value		85
#define RCC_PLLCFGR_PLLN_MUL86_value		86
#define RCC_PLLCFGR_PLLN_MUL87_value		87
#define RCC_PLLCFGR_PLLN_MUL88_value		88
#define RCC_PLLCFGR_PLLN_MUL89_value		89
#define RCC_PLLCFGR_PLLN_MUL90_value		90
#define RCC_PLLCFGR_PLLN_MUL91_value		91
#define RCC_PLLCFGR_PLLN_MUL92_value		92
#define RCC_PLLCFGR_PLLN_MUL93_value		93
#define RCC_PLLCFGR_PLLN_MUL94_value		94
#define RCC_PLLCFGR_PLLN_MUL95_value		95
#define RCC_PLLCFGR_PLLN_MUL96_value		96
#define RCC_PLLCFGR_PLLN_MUL97_value		97
#define RCC_PLLCFGR_PLLN_MUL98_value		98
#define RCC_PLLCFGR_PLLN_MUL99_value		99
#define RCC_PLLCFGR_PLLN_MUL100_value		100
#define RCC_PLLCFGR_PLLN_MUL101_value		101
#define RCC_PLLCFGR_PLLN_MUL102_value		102
#define RCC_PLLCFGR_PLLN_MUL103_value		103
#define RCC_PLLCFGR_PLLN_MUL104_value		104
#define RCC_PLLCFGR_PLLN_MUL105_value		105
#define RCC_PLLCFGR_PLLN_MUL106_value		106
#define RCC_PLLCFGR_PLLN_MUL107_value		107
#define RCC_PLLCFGR_PLLN_MUL108_value		108
#define RCC_PLLCFGR_PLLN_MUL109_value		109
#define RCC_PLLCFGR_PLLN_MUL110_value		110
#define RCC_PLLCFGR_PLLN_MUL111_value		111
#define RCC_PLLCFGR_PLLN_MUL112_value		112
#define RCC_PLLCFGR_PLLN_MUL113_value		113
#define RCC_PLLCFGR_PLLN_MUL114_value		114
#define RCC_PLLCFGR_PLLN_MUL115_value		115
#define RCC_PLLCFGR_PLLN_MUL116_value		116
#define RCC_PLLCFGR_PLLN_MUL117_value		117
#define RCC_PLLCFGR_PLLN_MUL118_value		118
#define RCC_PLLCFGR_PLLN_MUL119_value		119
#define RCC_PLLCFGR_PLLN_MUL120_value		120
#define RCC_PLLCFGR_PLLN_MUL121_value		121
#define RCC_PLLCFGR_PLLN_MUL122_value		122
#define RCC_PLLCFGR_PLLN_MUL123_value		123
#define RCC_PLLCFGR_PLLN_MUL124_value		124
#define RCC_PLLCFGR_PLLN_MUL125_value		125
#define RCC_PLLCFGR_PLLN_MUL126_value		126
#define RCC_PLLCFGR_PLLN_MUL127_value		127
#define RCC_PLLCFGR_PLLN_MUL128_value		128
#define RCC_PLLCFGR_PLLN_MUL129_value		129
#define RCC_PLLCFGR_PLLN_MUL130_value		130
#define RCC_PLLCFGR_PLLN_MUL131_value		131
#define RCC_PLLCFGR_PLLN_MUL132_value		132
#define RCC_PLLCFGR_PLLN_MUL133_value		133
#define RCC_PLLCFGR_PLLN_MUL134_value		134
#define RCC_PLLCFGR_PLLN_MUL135_value		135
#define RCC_PLLCFGR_PLLN_MUL136_value		136
#define RCC_PLLCFGR_PLLN_MUL137_value		137
#define RCC_PLLCFGR_PLLN_MUL138_value		138
#define RCC_PLLCFGR_PLLN_MUL139_value		139
#define RCC_PLLCFGR_PLLN_MUL140_value		140
#define RCC_PLLCFGR_PLLN_MUL141_value		141
#define RCC_PLLCFGR_PLLN_MUL142_value		142
#define RCC_PLLCFGR_PLLN_MUL143_value		143
#define RCC_PLLCFGR_PLLN_MUL144_value		144
#define RCC_PLLCFGR_PLLN_MUL145_value		145
#define RCC_PLLCFGR_PLLN_MUL146_value		146
#define RCC_PLLCFGR_PLLN_MUL147_value		147
#define RCC_PLLCFGR_PLLN_MUL148_value		148
#define RCC_PLLCFGR_PLLN_MUL149_value		149
#define RCC_PLLCFGR_PLLN_MUL150_value		150
#define RCC_PLLCFGR_PLLN_MUL151_value		151
#define RCC_PLLCFGR_PLLN_MUL152_value		152
#define RCC_PLLCFGR_PLLN_MUL153_value		153
#define RCC_PLLCFGR_PLLN_MUL154_value		154
#define RCC_PLLCFGR_PLLN_MUL155_value		155
#define RCC_PLLCFGR_PLLN_MUL156_value		156
#define RCC_PLLCFGR_PLLN_MUL157_value		157
#define RCC_PLLCFGR_PLLN_MUL158_value		158
#define RCC_PLLCFGR_PLLN_MUL159_value		159
#define RCC_PLLCFGR_PLLN_MUL160_value		160
#define RCC_PLLCFGR_PLLN_MUL161_value		161
#define RCC_PLLCFGR_PLLN_MUL162_value		162
#define RCC_PLLCFGR_PLLN_MUL163_value		163
#define RCC_PLLCFGR_PLLN_MUL164_value		164
#define RCC_PLLCFGR_PLLN_MUL165_value		165
#define RCC_PLLCFGR_PLLN_MUL166_value		166
#define RCC_PLLCFGR_PLLN_MUL167_value		167
#define RCC_PLLCFGR_PLLN_MUL168_value		168
#define RCC_PLLCFGR_PLLN_MUL169_value		169
#define RCC_PLLCFGR_PLLN_MUL170_value		170
#define RCC_PLLCFGR_PLLN_MUL171_value		171
#define RCC_PLLCFGR_PLLN_MUL172_value		172
#define RCC_PLLCFGR_PLLN_MUL173_value		173
#define RCC_PLLCFGR_PLLN_MUL174_value		174
#define RCC_PLLCFGR_PLLN_MUL175_value		175
#define RCC_PLLCFGR_PLLN_MUL176_value		176
#define RCC_PLLCFGR_PLLN_MUL177_value		177
#define RCC_PLLCFGR_PLLN_MUL178_value		178
#define RCC_PLLCFGR_PLLN_MUL179_value		179
#define RCC_PLLCFGR_PLLN_MUL180_value		180
#define RCC_PLLCFGR_PLLN_MUL181_value		181
#define RCC_PLLCFGR_PLLN_MUL182_value		182
#define RCC_PLLCFGR_PLLN_MUL183_value		183
#define RCC_PLLCFGR_PLLN_MUL184_value		184
#define RCC_PLLCFGR_PLLN_MUL185_value		185
#define RCC_PLLCFGR_PLLN_MUL186_value		186
#define RCC_PLLCFGR_PLLN_MUL187_value		187
#define RCC_PLLCFGR_PLLN_MUL188_value		188
#define RCC_PLLCFGR_PLLN_MUL189_value		189
#define RCC_PLLCFGR_PLLN_MUL190_value		190
#define RCC_PLLCFGR_PLLN_MUL191_value		191
#define RCC_PLLCFGR_PLLN_MUL192_value		192
#define RCC_PLLCFGR_PLLN_MUL193_value		193
#define RCC_PLLCFGR_PLLN_MUL194_value		194
#define RCC_PLLCFGR_PLLN_MUL195_value		195
#define RCC_PLLCFGR_PLLN_MUL196_value		196
#define RCC_PLLCFGR_PLLN_MUL197_value		197
#define RCC_PLLCFGR_PLLN_MUL198_value		198
#define RCC_PLLCFGR_PLLN_MUL199_value		199
#define RCC_PLLCFGR_PLLN_MUL200_value		200
#define RCC_PLLCFGR_PLLN_MUL201_value		201
#define RCC_PLLCFGR_PLLN_MUL202_value		202
#define RCC_PLLCFGR_PLLN_MUL203_value		203
#define RCC_PLLCFGR_PLLN_MUL204_value		204
#define RCC_PLLCFGR_PLLN_MUL205_value		205
#define RCC_PLLCFGR_PLLN_MUL206_value		206
#define RCC_PLLCFGR_PLLN_MUL207_value		207
#define RCC_PLLCFGR_PLLN_MUL208_value		208
#define RCC_PLLCFGR_PLLN_MUL209_value		209
#define RCC_PLLCFGR_PLLN_MUL210_value		210
#define RCC_PLLCFGR_PLLN_MUL211_value		211
#define RCC_PLLCFGR_PLLN_MUL212_value		212
#define RCC_PLLCFGR_PLLN_MUL213_value		213
#define RCC_PLLCFGR_PLLN_MUL214_value		214
#define RCC_PLLCFGR_PLLN_MUL215_value		215
#define RCC_PLLCFGR_PLLN_MUL216_value		216
#define RCC_PLLCFGR_PLLN_MUL217_value		217
#define RCC_PLLCFGR_PLLN_MUL218_value		218
#define RCC_PLLCFGR_PLLN_MUL219_value		219
#define RCC_PLLCFGR_PLLN_MUL220_value		220
#define RCC_PLLCFGR_PLLN_MUL221_value		221
#define RCC_PLLCFGR_PLLN_MUL222_value		222
#define RCC_PLLCFGR_PLLN_MUL223_value		223
#define RCC_PLLCFGR_PLLN_MUL224_value		224
#define RCC_PLLCFGR_PLLN_MUL225_value		225
#define RCC_PLLCFGR_PLLN_MUL226_value		226
#define RCC_PLLCFGR_PLLN_MUL227_value		227
#define RCC_PLLCFGR_PLLN_MUL228_value		228
#define RCC_PLLCFGR_PLLN_MUL229_value		229
#define RCC_PLLCFGR_PLLN_MUL230_value		230
#define RCC_PLLCFGR_PLLN_MUL231_value		231
#define RCC_PLLCFGR_PLLN_MUL232_value		232
#define RCC_PLLCFGR_PLLN_MUL233_value		233
#define RCC_PLLCFGR_PLLN_MUL234_value		234
#define RCC_PLLCFGR_PLLN_MUL235_value		235
#define RCC_PLLCFGR_PLLN_MUL236_value		236
#define RCC_PLLCFGR_PLLN_MUL237_value		237
#define RCC_PLLCFGR_PLLN_MUL238_value		238
#define RCC_PLLCFGR_PLLN_MUL239_value		239
#define RCC_PLLCFGR_PLLN_MUL240_value		240
#define RCC_PLLCFGR_PLLN_MUL241_value		241
#define RCC_PLLCFGR_PLLN_MUL242_value		242
#define RCC_PLLCFGR_PLLN_MUL243_value		243
#define RCC_PLLCFGR_PLLN_MUL244_value		244
#define RCC_PLLCFGR_PLLN_MUL245_value		245
#define RCC_PLLCFGR_PLLN_MUL246_value		246
#define RCC_PLLCFGR_PLLN_MUL247_value		247
#define RCC_PLLCFGR_PLLN_MUL248_value		248
#define RCC_PLLCFGR_PLLN_MUL249_value		249
#define RCC_PLLCFGR_PLLN_MUL250_value		250
#define RCC_PLLCFGR_PLLN_MUL251_value		251
#define RCC_PLLCFGR_PLLN_MUL252_value		252
#define RCC_PLLCFGR_PLLN_MUL253_value		253
#define RCC_PLLCFGR_PLLN_MUL254_value		254
#define RCC_PLLCFGR_PLLN_MUL255_value		255
#define RCC_PLLCFGR_PLLN_MUL256_value		256
#define RCC_PLLCFGR_PLLN_MUL257_value		257
#define RCC_PLLCFGR_PLLN_MUL258_value		258
#define RCC_PLLCFGR_PLLN_MUL259_value		259
#define RCC_PLLCFGR_PLLN_MUL260_value		260
#define RCC_PLLCFGR_PLLN_MUL261_value		261
#define RCC_PLLCFGR_PLLN_MUL262_value		262
#define RCC_PLLCFGR_PLLN_MUL263_value		263
#define RCC_PLLCFGR_PLLN_MUL264_value		264
#define RCC_PLLCFGR_PLLN_MUL265_value		265
#define RCC_PLLCFGR_PLLN_MUL266_value		266
#define RCC_PLLCFGR_PLLN_MUL267_value		267
#define RCC_PLLCFGR_PLLN_MUL268_value		268
#define RCC_PLLCFGR_PLLN_MUL269_value		269
#define RCC_PLLCFGR_PLLN_MUL270_value		270
#define RCC_PLLCFGR_PLLN_MUL271_value		271
#define RCC_PLLCFGR_PLLN_MUL272_value		272
#define RCC_PLLCFGR_PLLN_MUL273_value		273
#define RCC_PLLCFGR_PLLN_MUL274_value		274
#define RCC_PLLCFGR_PLLN_MUL275_value		275
#define RCC_PLLCFGR_PLLN_MUL276_value		276
#define RCC_PLLCFGR_PLLN_MUL277_value		277
#define RCC_PLLCFGR_PLLN_MUL278_value		278
#define RCC_PLLCFGR_PLLN_MUL279_value		279
#define RCC_PLLCFGR_PLLN_MUL280_value		280
#define RCC_PLLCFGR_PLLN_MUL281_value		281
#define RCC_PLLCFGR_PLLN_MUL282_value		282
#define RCC_PLLCFGR_PLLN_MUL283_value		283
#define RCC_PLLCFGR_PLLN_MUL284_value		284
#define RCC_PLLCFGR_PLLN_MUL285_value		285
#define RCC_PLLCFGR_PLLN_MUL286_value		286
#define RCC_PLLCFGR_PLLN_MUL287_value		287
#define RCC_PLLCFGR_PLLN_MUL288_value		288
#define RCC_PLLCFGR_PLLN_MUL289_value		289
#define RCC_PLLCFGR_PLLN_MUL290_value		290
#define RCC_PLLCFGR_PLLN_MUL291_value		291
#define RCC_PLLCFGR_PLLN_MUL292_value		292
#define RCC_PLLCFGR_PLLN_MUL293_value		293
#define RCC_PLLCFGR_PLLN_MUL294_value		294
#define RCC_PLLCFGR_PLLN_MUL295_value		295
#define RCC_PLLCFGR_PLLN_MUL296_value		296
#define RCC_PLLCFGR_PLLN_MUL297_value		297
#define RCC_PLLCFGR_PLLN_MUL298_value		298
#define RCC_PLLCFGR_PLLN_MUL299_value		299
#define RCC_PLLCFGR_PLLN_MUL300_value		300
#define RCC_PLLCFGR_PLLN_MUL301_value		301
#define RCC_PLLCFGR_PLLN_MUL302_value		302
#define RCC_PLLCFGR_PLLN_MUL303_value		303
#define RCC_PLLCFGR_PLLN_MUL304_value		304
#define RCC_PLLCFGR_PLLN_MUL305_value		305
#define RCC_PLLCFGR_PLLN_MUL306_value		306
#define RCC_PLLCFGR_PLLN_MUL307_value		307
#define RCC_PLLCFGR_PLLN_MUL308_value		308
#define RCC_PLLCFGR_PLLN_MUL309_value		309
#define RCC_PLLCFGR_PLLN_MUL310_value		310
#define RCC_PLLCFGR_PLLN_MUL311_value		311
#define RCC_PLLCFGR_PLLN_MUL312_value		312
#define RCC_PLLCFGR_PLLN_MUL313_value		313
#define RCC_PLLCFGR_PLLN_MUL314_value		314
#define RCC_PLLCFGR_PLLN_MUL315_value		315
#define RCC_PLLCFGR_PLLN_MUL316_value		316
#define RCC_PLLCFGR_PLLN_MUL317_value		317
#define RCC_PLLCFGR_PLLN_MUL318_value		318
#define RCC_PLLCFGR_PLLN_MUL319_value		319
#define RCC_PLLCFGR_PLLN_MUL320_value		320
#define RCC_PLLCFGR_PLLN_MUL321_value		321
#define RCC_PLLCFGR_PLLN_MUL322_value		322
#define RCC_PLLCFGR_PLLN_MUL323_value		323
#define RCC_PLLCFGR_PLLN_MUL324_value		324
#define RCC_PLLCFGR_PLLN_MUL325_value		325
#define RCC_PLLCFGR_PLLN_MUL326_value		326
#define RCC_PLLCFGR_PLLN_MUL327_value		327
#define RCC_PLLCFGR_PLLN_MUL328_value		328
#define RCC_PLLCFGR_PLLN_MUL329_value		329
#define RCC_PLLCFGR_PLLN_MUL330_value		330
#define RCC_PLLCFGR_PLLN_MUL331_value		331
#define RCC_PLLCFGR_PLLN_MUL332_value		332
#define RCC_PLLCFGR_PLLN_MUL333_value		333
#define RCC_PLLCFGR_PLLN_MUL334_value		334
#define RCC_PLLCFGR_PLLN_MUL335_value		335
#define RCC_PLLCFGR_PLLN_MUL336_value		336
#define RCC_PLLCFGR_PLLN_MUL337_value		337
#define RCC_PLLCFGR_PLLN_MUL338_value		338
#define RCC_PLLCFGR_PLLN_MUL339_value		339
#define RCC_PLLCFGR_PLLN_MUL340_value		340
#define RCC_PLLCFGR_PLLN_MUL341_value		341
#define RCC_PLLCFGR_PLLN_MUL342_value		342
#define RCC_PLLCFGR_PLLN_MUL343_value		343
#define RCC_PLLCFGR_PLLN_MUL344_value		344
#define RCC_PLLCFGR_PLLN_MUL345_value		345
#define RCC_PLLCFGR_PLLN_MUL346_value		346
#define RCC_PLLCFGR_PLLN_MUL347_value		347
#define RCC_PLLCFGR_PLLN_MUL348_value		348
#define RCC_PLLCFGR_PLLN_MUL349_value		349
#define RCC_PLLCFGR_PLLN_MUL350_value		350
#define RCC_PLLCFGR_PLLN_MUL351_value		351
#define RCC_PLLCFGR_PLLN_MUL352_value		352
#define RCC_PLLCFGR_PLLN_MUL353_value		353
#define RCC_PLLCFGR_PLLN_MUL354_value		354
#define RCC_PLLCFGR_PLLN_MUL355_value		355
#define RCC_PLLCFGR_PLLN_MUL356_value		356
#define RCC_PLLCFGR_PLLN_MUL357_value		357
#define RCC_PLLCFGR_PLLN_MUL358_value		358
#define RCC_PLLCFGR_PLLN_MUL359_value		359
#define RCC_PLLCFGR_PLLN_MUL360_value		360
#define RCC_PLLCFGR_PLLN_MUL361_value		361
#define RCC_PLLCFGR_PLLN_MUL362_value		362
#define RCC_PLLCFGR_PLLN_MUL363_value		363
#define RCC_PLLCFGR_PLLN_MUL364_value		364
#define RCC_PLLCFGR_PLLN_MUL365_value		365
#define RCC_PLLCFGR_PLLN_MUL366_value		366
#define RCC_PLLCFGR_PLLN_MUL367_value		367
#define RCC_PLLCFGR_PLLN_MUL368_value		368
#define RCC_PLLCFGR_PLLN_MUL369_value		369
#define RCC_PLLCFGR_PLLN_MUL370_value		370
#define RCC_PLLCFGR_PLLN_MUL371_value		371
#define RCC_PLLCFGR_PLLN_MUL372_value		372
#define RCC_PLLCFGR_PLLN_MUL373_value		373
#define RCC_PLLCFGR_PLLN_MUL374_value		374
#define RCC_PLLCFGR_PLLN_MUL375_value		375
#define RCC_PLLCFGR_PLLN_MUL376_value		376
#define RCC_PLLCFGR_PLLN_MUL377_value		377
#define RCC_PLLCFGR_PLLN_MUL378_value		378
#define RCC_PLLCFGR_PLLN_MUL379_value		379
#define RCC_PLLCFGR_PLLN_MUL380_value		380
#define RCC_PLLCFGR_PLLN_MUL381_value		381
#define RCC_PLLCFGR_PLLN_MUL382_value		382
#define RCC_PLLCFGR_PLLN_MUL383_value		383
#define RCC_PLLCFGR_PLLN_MUL384_value		384
#define RCC_PLLCFGR_PLLN_MUL385_value		385
#define RCC_PLLCFGR_PLLN_MUL386_value		386
#define RCC_PLLCFGR_PLLN_MUL387_value		387
#define RCC_PLLCFGR_PLLN_MUL388_value		388
#define RCC_PLLCFGR_PLLN_MUL389_value		389
#define RCC_PLLCFGR_PLLN_MUL390_value		390
#define RCC_PLLCFGR_PLLN_MUL391_value		391
#define RCC_PLLCFGR_PLLN_MUL392_value		392
#define RCC_PLLCFGR_PLLN_MUL393_value		393
#define RCC_PLLCFGR_PLLN_MUL394_value		394
#define RCC_PLLCFGR_PLLN_MUL395_value		395
#define RCC_PLLCFGR_PLLN_MUL396_value		396
#define RCC_PLLCFGR_PLLN_MUL397_value		397
#define RCC_PLLCFGR_PLLN_MUL398_value		398
#define RCC_PLLCFGR_PLLN_MUL399_value		399
#define RCC_PLLCFGR_PLLN_MUL400_value		400
#define RCC_PLLCFGR_PLLN_MUL401_value		401
#define RCC_PLLCFGR_PLLN_MUL402_value		402
#define RCC_PLLCFGR_PLLN_MUL403_value		403
#define RCC_PLLCFGR_PLLN_MUL404_value		404
#define RCC_PLLCFGR_PLLN_MUL405_value		405
#define RCC_PLLCFGR_PLLN_MUL406_value		406
#define RCC_PLLCFGR_PLLN_MUL407_value		407
#define RCC_PLLCFGR_PLLN_MUL408_value		408
#define RCC_PLLCFGR_PLLN_MUL409_value		409
#define RCC_PLLCFGR_PLLN_MUL410_value		410
#define RCC_PLLCFGR_PLLN_MUL411_value		411
#define RCC_PLLCFGR_PLLN_MUL412_value		412
#define RCC_PLLCFGR_PLLN_MUL413_value		413
#define RCC_PLLCFGR_PLLN_MUL414_value		414
#define RCC_PLLCFGR_PLLN_MUL415_value		415
#define RCC_PLLCFGR_PLLN_MUL416_value		416
#define RCC_PLLCFGR_PLLN_MUL417_value		417
#define RCC_PLLCFGR_PLLN_MUL418_value		418
#define RCC_PLLCFGR_PLLN_MUL419_value		419
#define RCC_PLLCFGR_PLLN_MUL420_value		420
#define RCC_PLLCFGR_PLLN_MUL421_value		421
#define RCC_PLLCFGR_PLLN_MUL422_value		422
#define RCC_PLLCFGR_PLLN_MUL423_value		423
#define RCC_PLLCFGR_PLLN_MUL424_value		424
#define RCC_PLLCFGR_PLLN_MUL425_value		425
#define RCC_PLLCFGR_PLLN_MUL426_value		426
#define RCC_PLLCFGR_PLLN_MUL427_value		427
#define RCC_PLLCFGR_PLLN_MUL428_value		428
#define RCC_PLLCFGR_PLLN_MUL429_value		429
#define RCC_PLLCFGR_PLLN_MUL430_value		430
#define RCC_PLLCFGR_PLLN_MUL431_value		431
#define RCC_PLLCFGR_PLLN_MUL432_value		432
#define RCC_PLLCFGR_PLLN_mask				511

#define RCC_PLLCFGR_PLLM_DIV2_value			2
#define RCC_PLLCFGR_PLLM_DIV3_value			3
#define RCC_PLLCFGR_PLLM_DIV4_value			4
#define RCC_PLLCFGR_PLLM_DIV5_value			5
#define RCC_PLLCFGR_PLLM_DIV6_value			6
#define RCC_PLLCFGR_PLLM_DIV7_value			7
#define RCC_PLLCFGR_PLLM_DIV8_value			8
#define RCC_PLLCFGR_PLLM_DIV9_value			9
#define RCC_PLLCFGR_PLLM_DIV10_value		10
#define RCC_PLLCFGR_PLLM_DIV11_value		11
#define RCC_PLLCFGR_PLLM_DIV12_value		12
#define RCC_PLLCFGR_PLLM_DIV13_value		13
#define RCC_PLLCFGR_PLLM_DIV14_value		14
#define RCC_PLLCFGR_PLLM_DIV15_value		15
#define RCC_PLLCFGR_PLLM_DIV16_value		16
#define RCC_PLLCFGR_PLLM_DIV17_value		17
#define RCC_PLLCFGR_PLLM_DIV18_value		18
#define RCC_PLLCFGR_PLLM_DIV19_value		19
#define RCC_PLLCFGR_PLLM_DIV20_value		20
#define RCC_PLLCFGR_PLLM_DIV21_value		21
#define RCC_PLLCFGR_PLLM_DIV22_value		22
#define RCC_PLLCFGR_PLLM_DIV23_value		23
#define RCC_PLLCFGR_PLLM_DIV24_value		24
#define RCC_PLLCFGR_PLLM_DIV25_value		25
#define RCC_PLLCFGR_PLLM_DIV26_value		26
#define RCC_PLLCFGR_PLLM_DIV27_value		27
#define RCC_PLLCFGR_PLLM_DIV28_value		28
#define RCC_PLLCFGR_PLLM_DIV29_value		29
#define RCC_PLLCFGR_PLLM_DIV30_value		30
#define RCC_PLLCFGR_PLLM_DIV31_value		31
#define RCC_PLLCFGR_PLLM_DIV32_value		32
#define RCC_PLLCFGR_PLLM_DIV33_value		33
#define RCC_PLLCFGR_PLLM_DIV34_value		34
#define RCC_PLLCFGR_PLLM_DIV35_value		35
#define RCC_PLLCFGR_PLLM_DIV36_value		36
#define RCC_PLLCFGR_PLLM_DIV37_value		37
#define RCC_PLLCFGR_PLLM_DIV38_value		38
#define RCC_PLLCFGR_PLLM_DIV39_value		39
#define RCC_PLLCFGR_PLLM_DIV40_value		40
#define RCC_PLLCFGR_PLLM_DIV41_value		41
#define RCC_PLLCFGR_PLLM_DIV42_value		42
#define RCC_PLLCFGR_PLLM_DIV43_value		43
#define RCC_PLLCFGR_PLLM_DIV44_value		44
#define RCC_PLLCFGR_PLLM_DIV45_value		45
#define RCC_PLLCFGR_PLLM_DIV46_value		46
#define RCC_PLLCFGR_PLLM_DIV47_value		47
#define RCC_PLLCFGR_PLLM_DIV48_value		48
#define RCC_PLLCFGR_PLLM_DIV49_value		49
#define RCC_PLLCFGR_PLLM_DIV50_value		50
#define RCC_PLLCFGR_PLLM_DIV51_value		51
#define RCC_PLLCFGR_PLLM_DIV52_value		52
#define RCC_PLLCFGR_PLLM_DIV53_value		53
#define RCC_PLLCFGR_PLLM_DIV54_value		54
#define RCC_PLLCFGR_PLLM_DIV55_value		55
#define RCC_PLLCFGR_PLLM_DIV56_value		56
#define RCC_PLLCFGR_PLLM_DIV57_value		57
#define RCC_PLLCFGR_PLLM_DIV58_value		58
#define RCC_PLLCFGR_PLLM_DIV59_value		59
#define RCC_PLLCFGR_PLLM_DIV60_value		60
#define RCC_PLLCFGR_PLLM_DIV61_value		61
#define RCC_PLLCFGR_PLLM_DIV62_value		62
#define RCC_PLLCFGR_PLLM_DIV63_value		63
#define RCC_PLLCFGR_PLLM_mask				63

#define RCC_PLLCFGR_PLLQ_DIV2				(RCC_PLLCFGR_PLLQ_DIV2_value << RCC_PLLCFGR_PLLQ_bit)
#define RCC_PLLCFGR_PLLQ_DIV3				(RCC_PLLCFGR_PLLQ_DIV3_value << RCC_PLLCFGR_PLLQ_bit)
#define RCC_PLLCFGR_PLLQ_DIV4				(RCC_PLLCFGR_PLLQ_DIV4_value << RCC_PLLCFGR_PLLQ_bit)
#define RCC_PLLCFGR_PLLQ_DIV5				(RCC_PLLCFGR_PLLQ_DIV5_value << RCC_PLLCFGR_PLLQ_bit)
#define RCC_PLLCFGR_PLLQ_DIV6				(RCC_PLLCFGR_PLLQ_DIV6_value << RCC_PLLCFGR_PLLQ_bit)
#define RCC_PLLCFGR_PLLQ_DIV7				(RCC_PLLCFGR_PLLQ_DIV7_value << RCC_PLLCFGR_PLLQ_bit)
#define RCC_PLLCFGR_PLLQ_DIV8				(RCC_PLLCFGR_PLLQ_DIV8_value << RCC_PLLCFGR_PLLQ_bit)
#define RCC_PLLCFGR_PLLQ_DIV9				(RCC_PLLCFGR_PLLQ_DIV9_value << RCC_PLLCFGR_PLLQ_bit)
#define RCC_PLLCFGR_PLLQ_DIV10				(RCC_PLLCFGR_PLLQ_DIV10_value << RCC_PLLCFGR_PLLQ_bit)
#define RCC_PLLCFGR_PLLQ_DIV11				(RCC_PLLCFGR_PLLQ_DIV11_value << RCC_PLLCFGR_PLLQ_bit)
#define RCC_PLLCFGR_PLLQ_DIV12				(RCC_PLLCFGR_PLLQ_DIV12_value << RCC_PLLCFGR_PLLQ_bit)
#define RCC_PLLCFGR_PLLQ_DIV13				(RCC_PLLCFGR_PLLQ_DIV13_value << RCC_PLLCFGR_PLLQ_bit)
#define RCC_PLLCFGR_PLLQ_DIV14				(RCC_PLLCFGR_PLLQ_DIV14_value << RCC_PLLCFGR_PLLQ_bit)
#define RCC_PLLCFGR_PLLQ_DIV15				(RCC_PLLCFGR_PLLQ_DIV15_value << RCC_PLLCFGR_PLLQ_bit)

#define RCC_PLLCFGR_PLLP_DIV2				(RCC_PLLCFGR_PLLP_DIV2_value << RCC_PLLCFGR_PLLP_bit)
#define RCC_PLLCFGR_PLLP_DIV4				(RCC_PLLCFGR_PLLP_DIV4_value << RCC_PLLCFGR_PLLP_bit)
#define RCC_PLLCFGR_PLLP_DIV6				(RCC_PLLCFGR_PLLP_DIV6_value << RCC_PLLCFGR_PLLP_bit)
#define RCC_PLLCFGR_PLLP_DIV8				(RCC_PLLCFGR_PLLP_DIV8_value << RCC_PLLCFGR_PLLP_bit)

#define RCC_PLLCFGR_PLLN_MUL64				(RCC_PLLCFGR_PLLN_MUL64_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL65				(RCC_PLLCFGR_PLLN_MUL65_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL66				(RCC_PLLCFGR_PLLN_MUL66_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL67				(RCC_PLLCFGR_PLLN_MUL67_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL68				(RCC_PLLCFGR_PLLN_MUL68_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL69				(RCC_PLLCFGR_PLLN_MUL69_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL70				(RCC_PLLCFGR_PLLN_MUL70_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL71				(RCC_PLLCFGR_PLLN_MUL71_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL72				(RCC_PLLCFGR_PLLN_MUL72_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL73				(RCC_PLLCFGR_PLLN_MUL73_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL74				(RCC_PLLCFGR_PLLN_MUL74_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL75				(RCC_PLLCFGR_PLLN_MUL75_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL76				(RCC_PLLCFGR_PLLN_MUL76_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL77				(RCC_PLLCFGR_PLLN_MUL77_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL78				(RCC_PLLCFGR_PLLN_MUL78_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL79				(RCC_PLLCFGR_PLLN_MUL79_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL80				(RCC_PLLCFGR_PLLN_MUL80_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL81				(RCC_PLLCFGR_PLLN_MUL81_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL82				(RCC_PLLCFGR_PLLN_MUL82_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL83				(RCC_PLLCFGR_PLLN_MUL83_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL84				(RCC_PLLCFGR_PLLN_MUL84_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL85				(RCC_PLLCFGR_PLLN_MUL85_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL86				(RCC_PLLCFGR_PLLN_MUL86_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL87				(RCC_PLLCFGR_PLLN_MUL87_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL88				(RCC_PLLCFGR_PLLN_MUL88_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL89				(RCC_PLLCFGR_PLLN_MUL89_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL90				(RCC_PLLCFGR_PLLN_MUL90_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL91				(RCC_PLLCFGR_PLLN_MUL91_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL92				(RCC_PLLCFGR_PLLN_MUL92_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL93				(RCC_PLLCFGR_PLLN_MUL93_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL94				(RCC_PLLCFGR_PLLN_MUL94_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL95				(RCC_PLLCFGR_PLLN_MUL95_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL96				(RCC_PLLCFGR_PLLN_MUL96_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL97				(RCC_PLLCFGR_PLLN_MUL97_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL98				(RCC_PLLCFGR_PLLN_MUL98_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL99				(RCC_PLLCFGR_PLLN_MUL99_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL100				(RCC_PLLCFGR_PLLN_MUL100_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL101				(RCC_PLLCFGR_PLLN_MUL101_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL102				(RCC_PLLCFGR_PLLN_MUL102_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL103				(RCC_PLLCFGR_PLLN_MUL103_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL104				(RCC_PLLCFGR_PLLN_MUL104_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL105				(RCC_PLLCFGR_PLLN_MUL105_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL106				(RCC_PLLCFGR_PLLN_MUL106_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL107				(RCC_PLLCFGR_PLLN_MUL107_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL108				(RCC_PLLCFGR_PLLN_MUL108_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL109				(RCC_PLLCFGR_PLLN_MUL109_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL110				(RCC_PLLCFGR_PLLN_MUL110_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL111				(RCC_PLLCFGR_PLLN_MUL111_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL112				(RCC_PLLCFGR_PLLN_MUL112_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL113				(RCC_PLLCFGR_PLLN_MUL113_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL114				(RCC_PLLCFGR_PLLN_MUL114_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL115				(RCC_PLLCFGR_PLLN_MUL115_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL116				(RCC_PLLCFGR_PLLN_MUL116_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL117				(RCC_PLLCFGR_PLLN_MUL117_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL118				(RCC_PLLCFGR_PLLN_MUL118_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL119				(RCC_PLLCFGR_PLLN_MUL119_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL120				(RCC_PLLCFGR_PLLN_MUL120_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL121				(RCC_PLLCFGR_PLLN_MUL121_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL122				(RCC_PLLCFGR_PLLN_MUL122_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL123				(RCC_PLLCFGR_PLLN_MUL123_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL124				(RCC_PLLCFGR_PLLN_MUL124_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL125				(RCC_PLLCFGR_PLLN_MUL125_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL126				(RCC_PLLCFGR_PLLN_MUL126_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL127				(RCC_PLLCFGR_PLLN_MUL127_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL128				(RCC_PLLCFGR_PLLN_MUL128_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL129				(RCC_PLLCFGR_PLLN_MUL129_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL130				(RCC_PLLCFGR_PLLN_MUL130_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL131				(RCC_PLLCFGR_PLLN_MUL131_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL132				(RCC_PLLCFGR_PLLN_MUL132_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL133				(RCC_PLLCFGR_PLLN_MUL133_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL134				(RCC_PLLCFGR_PLLN_MUL134_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL135				(RCC_PLLCFGR_PLLN_MUL135_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL136				(RCC_PLLCFGR_PLLN_MUL136_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL137				(RCC_PLLCFGR_PLLN_MUL137_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL138				(RCC_PLLCFGR_PLLN_MUL138_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL139				(RCC_PLLCFGR_PLLN_MUL139_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL140				(RCC_PLLCFGR_PLLN_MUL140_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL141				(RCC_PLLCFGR_PLLN_MUL141_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL142				(RCC_PLLCFGR_PLLN_MUL142_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL143				(RCC_PLLCFGR_PLLN_MUL143_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL144				(RCC_PLLCFGR_PLLN_MUL144_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL145				(RCC_PLLCFGR_PLLN_MUL145_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL146				(RCC_PLLCFGR_PLLN_MUL146_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL147				(RCC_PLLCFGR_PLLN_MUL147_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL148				(RCC_PLLCFGR_PLLN_MUL148_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL149				(RCC_PLLCFGR_PLLN_MUL149_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL150				(RCC_PLLCFGR_PLLN_MUL150_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL151				(RCC_PLLCFGR_PLLN_MUL151_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL152				(RCC_PLLCFGR_PLLN_MUL152_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL153				(RCC_PLLCFGR_PLLN_MUL153_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL154				(RCC_PLLCFGR_PLLN_MUL154_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL155				(RCC_PLLCFGR_PLLN_MUL155_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL156				(RCC_PLLCFGR_PLLN_MUL156_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL157				(RCC_PLLCFGR_PLLN_MUL157_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL158				(RCC_PLLCFGR_PLLN_MUL158_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL159				(RCC_PLLCFGR_PLLN_MUL159_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL160				(RCC_PLLCFGR_PLLN_MUL160_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL161				(RCC_PLLCFGR_PLLN_MUL161_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL162				(RCC_PLLCFGR_PLLN_MUL162_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL163				(RCC_PLLCFGR_PLLN_MUL163_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL164				(RCC_PLLCFGR_PLLN_MUL164_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL165				(RCC_PLLCFGR_PLLN_MUL165_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL166				(RCC_PLLCFGR_PLLN_MUL166_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL167				(RCC_PLLCFGR_PLLN_MUL167_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL168				(RCC_PLLCFGR_PLLN_MUL168_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL169				(RCC_PLLCFGR_PLLN_MUL169_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL170				(RCC_PLLCFGR_PLLN_MUL170_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL171				(RCC_PLLCFGR_PLLN_MUL171_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL172				(RCC_PLLCFGR_PLLN_MUL172_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL173				(RCC_PLLCFGR_PLLN_MUL173_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL174				(RCC_PLLCFGR_PLLN_MUL174_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL175				(RCC_PLLCFGR_PLLN_MUL175_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL176				(RCC_PLLCFGR_PLLN_MUL176_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL177				(RCC_PLLCFGR_PLLN_MUL177_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL178				(RCC_PLLCFGR_PLLN_MUL178_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL179				(RCC_PLLCFGR_PLLN_MUL179_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL180				(RCC_PLLCFGR_PLLN_MUL180_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL181				(RCC_PLLCFGR_PLLN_MUL181_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL182				(RCC_PLLCFGR_PLLN_MUL182_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL183				(RCC_PLLCFGR_PLLN_MUL183_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL184				(RCC_PLLCFGR_PLLN_MUL184_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL185				(RCC_PLLCFGR_PLLN_MUL185_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL186				(RCC_PLLCFGR_PLLN_MUL186_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL187				(RCC_PLLCFGR_PLLN_MUL187_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL188				(RCC_PLLCFGR_PLLN_MUL188_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL189				(RCC_PLLCFGR_PLLN_MUL189_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL190				(RCC_PLLCFGR_PLLN_MUL190_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL191				(RCC_PLLCFGR_PLLN_MUL191_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL192				(RCC_PLLCFGR_PLLN_MUL192_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL193				(RCC_PLLCFGR_PLLN_MUL193_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL194				(RCC_PLLCFGR_PLLN_MUL194_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL195				(RCC_PLLCFGR_PLLN_MUL195_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL196				(RCC_PLLCFGR_PLLN_MUL196_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL197				(RCC_PLLCFGR_PLLN_MUL197_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL198				(RCC_PLLCFGR_PLLN_MUL198_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL199				(RCC_PLLCFGR_PLLN_MUL199_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL200				(RCC_PLLCFGR_PLLN_MUL200_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL201				(RCC_PLLCFGR_PLLN_MUL201_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL202				(RCC_PLLCFGR_PLLN_MUL202_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL203				(RCC_PLLCFGR_PLLN_MUL203_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL204				(RCC_PLLCFGR_PLLN_MUL204_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL205				(RCC_PLLCFGR_PLLN_MUL205_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL206				(RCC_PLLCFGR_PLLN_MUL206_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL207				(RCC_PLLCFGR_PLLN_MUL207_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL208				(RCC_PLLCFGR_PLLN_MUL208_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL209				(RCC_PLLCFGR_PLLN_MUL209_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL210				(RCC_PLLCFGR_PLLN_MUL210_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL211				(RCC_PLLCFGR_PLLN_MUL211_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL212				(RCC_PLLCFGR_PLLN_MUL212_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL213				(RCC_PLLCFGR_PLLN_MUL213_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL214				(RCC_PLLCFGR_PLLN_MUL214_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL215				(RCC_PLLCFGR_PLLN_MUL215_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL216				(RCC_PLLCFGR_PLLN_MUL216_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL217				(RCC_PLLCFGR_PLLN_MUL217_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL218				(RCC_PLLCFGR_PLLN_MUL218_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL219				(RCC_PLLCFGR_PLLN_MUL219_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL220				(RCC_PLLCFGR_PLLN_MUL220_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL221				(RCC_PLLCFGR_PLLN_MUL221_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL222				(RCC_PLLCFGR_PLLN_MUL222_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL223				(RCC_PLLCFGR_PLLN_MUL223_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL224				(RCC_PLLCFGR_PLLN_MUL224_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL225				(RCC_PLLCFGR_PLLN_MUL225_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL226				(RCC_PLLCFGR_PLLN_MUL226_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL227				(RCC_PLLCFGR_PLLN_MUL227_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL228				(RCC_PLLCFGR_PLLN_MUL228_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL229				(RCC_PLLCFGR_PLLN_MUL229_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL230				(RCC_PLLCFGR_PLLN_MUL230_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL231				(RCC_PLLCFGR_PLLN_MUL231_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL232				(RCC_PLLCFGR_PLLN_MUL232_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL233				(RCC_PLLCFGR_PLLN_MUL233_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL234				(RCC_PLLCFGR_PLLN_MUL234_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL235				(RCC_PLLCFGR_PLLN_MUL235_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL236				(RCC_PLLCFGR_PLLN_MUL236_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL237				(RCC_PLLCFGR_PLLN_MUL237_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL238				(RCC_PLLCFGR_PLLN_MUL238_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL239				(RCC_PLLCFGR_PLLN_MUL239_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL240				(RCC_PLLCFGR_PLLN_MUL240_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL241				(RCC_PLLCFGR_PLLN_MUL241_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL242				(RCC_PLLCFGR_PLLN_MUL242_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL243				(RCC_PLLCFGR_PLLN_MUL243_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL244				(RCC_PLLCFGR_PLLN_MUL244_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL245				(RCC_PLLCFGR_PLLN_MUL245_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL246				(RCC_PLLCFGR_PLLN_MUL246_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL247				(RCC_PLLCFGR_PLLN_MUL247_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL248				(RCC_PLLCFGR_PLLN_MUL248_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL249				(RCC_PLLCFGR_PLLN_MUL249_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL250				(RCC_PLLCFGR_PLLN_MUL250_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL251				(RCC_PLLCFGR_PLLN_MUL251_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL252				(RCC_PLLCFGR_PLLN_MUL252_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL253				(RCC_PLLCFGR_PLLN_MUL253_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL254				(RCC_PLLCFGR_PLLN_MUL254_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL255				(RCC_PLLCFGR_PLLN_MUL255_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL256				(RCC_PLLCFGR_PLLN_MUL256_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL257				(RCC_PLLCFGR_PLLN_MUL257_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL258				(RCC_PLLCFGR_PLLN_MUL258_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL259				(RCC_PLLCFGR_PLLN_MUL259_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL260				(RCC_PLLCFGR_PLLN_MUL260_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL261				(RCC_PLLCFGR_PLLN_MUL261_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL262				(RCC_PLLCFGR_PLLN_MUL262_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL263				(RCC_PLLCFGR_PLLN_MUL263_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL264				(RCC_PLLCFGR_PLLN_MUL264_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL265				(RCC_PLLCFGR_PLLN_MUL265_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL266				(RCC_PLLCFGR_PLLN_MUL266_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL267				(RCC_PLLCFGR_PLLN_MUL267_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL268				(RCC_PLLCFGR_PLLN_MUL268_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL269				(RCC_PLLCFGR_PLLN_MUL269_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL270				(RCC_PLLCFGR_PLLN_MUL270_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL271				(RCC_PLLCFGR_PLLN_MUL271_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL272				(RCC_PLLCFGR_PLLN_MUL272_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL273				(RCC_PLLCFGR_PLLN_MUL273_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL274				(RCC_PLLCFGR_PLLN_MUL274_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL275				(RCC_PLLCFGR_PLLN_MUL275_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL276				(RCC_PLLCFGR_PLLN_MUL276_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL277				(RCC_PLLCFGR_PLLN_MUL277_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL278				(RCC_PLLCFGR_PLLN_MUL278_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL279				(RCC_PLLCFGR_PLLN_MUL279_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL280				(RCC_PLLCFGR_PLLN_MUL280_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL281				(RCC_PLLCFGR_PLLN_MUL281_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL282				(RCC_PLLCFGR_PLLN_MUL282_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL283				(RCC_PLLCFGR_PLLN_MUL283_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL284				(RCC_PLLCFGR_PLLN_MUL284_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL285				(RCC_PLLCFGR_PLLN_MUL285_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL286				(RCC_PLLCFGR_PLLN_MUL286_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL287				(RCC_PLLCFGR_PLLN_MUL287_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL288				(RCC_PLLCFGR_PLLN_MUL288_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL289				(RCC_PLLCFGR_PLLN_MUL289_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL290				(RCC_PLLCFGR_PLLN_MUL290_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL291				(RCC_PLLCFGR_PLLN_MUL291_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL292				(RCC_PLLCFGR_PLLN_MUL292_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL293				(RCC_PLLCFGR_PLLN_MUL293_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL294				(RCC_PLLCFGR_PLLN_MUL294_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL295				(RCC_PLLCFGR_PLLN_MUL295_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL296				(RCC_PLLCFGR_PLLN_MUL296_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL297				(RCC_PLLCFGR_PLLN_MUL297_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL298				(RCC_PLLCFGR_PLLN_MUL298_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL299				(RCC_PLLCFGR_PLLN_MUL299_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL300				(RCC_PLLCFGR_PLLN_MUL300_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL301				(RCC_PLLCFGR_PLLN_MUL301_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL302				(RCC_PLLCFGR_PLLN_MUL302_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL303				(RCC_PLLCFGR_PLLN_MUL303_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL304				(RCC_PLLCFGR_PLLN_MUL304_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL305				(RCC_PLLCFGR_PLLN_MUL305_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL306				(RCC_PLLCFGR_PLLN_MUL306_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL307				(RCC_PLLCFGR_PLLN_MUL307_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL308				(RCC_PLLCFGR_PLLN_MUL308_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL309				(RCC_PLLCFGR_PLLN_MUL309_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL310				(RCC_PLLCFGR_PLLN_MUL310_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL311				(RCC_PLLCFGR_PLLN_MUL311_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL312				(RCC_PLLCFGR_PLLN_MUL312_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL313				(RCC_PLLCFGR_PLLN_MUL313_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL314				(RCC_PLLCFGR_PLLN_MUL314_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL315				(RCC_PLLCFGR_PLLN_MUL315_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL316				(RCC_PLLCFGR_PLLN_MUL316_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL317				(RCC_PLLCFGR_PLLN_MUL317_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL318				(RCC_PLLCFGR_PLLN_MUL318_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL319				(RCC_PLLCFGR_PLLN_MUL319_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL320				(RCC_PLLCFGR_PLLN_MUL320_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL321				(RCC_PLLCFGR_PLLN_MUL321_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL322				(RCC_PLLCFGR_PLLN_MUL322_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL323				(RCC_PLLCFGR_PLLN_MUL323_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL324				(RCC_PLLCFGR_PLLN_MUL324_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL325				(RCC_PLLCFGR_PLLN_MUL325_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL326				(RCC_PLLCFGR_PLLN_MUL326_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL327				(RCC_PLLCFGR_PLLN_MUL327_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL328				(RCC_PLLCFGR_PLLN_MUL328_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL329				(RCC_PLLCFGR_PLLN_MUL329_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL330				(RCC_PLLCFGR_PLLN_MUL330_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL331				(RCC_PLLCFGR_PLLN_MUL331_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL332				(RCC_PLLCFGR_PLLN_MUL332_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL333				(RCC_PLLCFGR_PLLN_MUL333_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL334				(RCC_PLLCFGR_PLLN_MUL334_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL335				(RCC_PLLCFGR_PLLN_MUL335_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL336				(RCC_PLLCFGR_PLLN_MUL336_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL337				(RCC_PLLCFGR_PLLN_MUL337_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL338				(RCC_PLLCFGR_PLLN_MUL338_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL339				(RCC_PLLCFGR_PLLN_MUL339_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL340				(RCC_PLLCFGR_PLLN_MUL340_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL341				(RCC_PLLCFGR_PLLN_MUL341_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL342				(RCC_PLLCFGR_PLLN_MUL342_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL343				(RCC_PLLCFGR_PLLN_MUL343_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL344				(RCC_PLLCFGR_PLLN_MUL344_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL345				(RCC_PLLCFGR_PLLN_MUL345_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL346				(RCC_PLLCFGR_PLLN_MUL346_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL347				(RCC_PLLCFGR_PLLN_MUL347_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL348				(RCC_PLLCFGR_PLLN_MUL348_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL349				(RCC_PLLCFGR_PLLN_MUL349_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL350				(RCC_PLLCFGR_PLLN_MUL350_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL351				(RCC_PLLCFGR_PLLN_MUL351_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL352				(RCC_PLLCFGR_PLLN_MUL352_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL353				(RCC_PLLCFGR_PLLN_MUL353_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL354				(RCC_PLLCFGR_PLLN_MUL354_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL355				(RCC_PLLCFGR_PLLN_MUL355_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL356				(RCC_PLLCFGR_PLLN_MUL356_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL357				(RCC_PLLCFGR_PLLN_MUL357_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL358				(RCC_PLLCFGR_PLLN_MUL358_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL359				(RCC_PLLCFGR_PLLN_MUL359_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL360				(RCC_PLLCFGR_PLLN_MUL360_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL361				(RCC_PLLCFGR_PLLN_MUL361_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL362				(RCC_PLLCFGR_PLLN_MUL362_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL363				(RCC_PLLCFGR_PLLN_MUL363_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL364				(RCC_PLLCFGR_PLLN_MUL364_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL365				(RCC_PLLCFGR_PLLN_MUL365_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL366				(RCC_PLLCFGR_PLLN_MUL366_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL367				(RCC_PLLCFGR_PLLN_MUL367_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL368				(RCC_PLLCFGR_PLLN_MUL368_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL369				(RCC_PLLCFGR_PLLN_MUL369_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL370				(RCC_PLLCFGR_PLLN_MUL370_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL371				(RCC_PLLCFGR_PLLN_MUL371_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL372				(RCC_PLLCFGR_PLLN_MUL372_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL373				(RCC_PLLCFGR_PLLN_MUL373_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL374				(RCC_PLLCFGR_PLLN_MUL374_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL375				(RCC_PLLCFGR_PLLN_MUL375_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL376				(RCC_PLLCFGR_PLLN_MUL376_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL377				(RCC_PLLCFGR_PLLN_MUL377_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL378				(RCC_PLLCFGR_PLLN_MUL378_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL379				(RCC_PLLCFGR_PLLN_MUL379_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL380				(RCC_PLLCFGR_PLLN_MUL380_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL381				(RCC_PLLCFGR_PLLN_MUL381_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL382				(RCC_PLLCFGR_PLLN_MUL382_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL383				(RCC_PLLCFGR_PLLN_MUL383_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL384				(RCC_PLLCFGR_PLLN_MUL384_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL385				(RCC_PLLCFGR_PLLN_MUL385_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL386				(RCC_PLLCFGR_PLLN_MUL386_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL387				(RCC_PLLCFGR_PLLN_MUL387_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL388				(RCC_PLLCFGR_PLLN_MUL388_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL389				(RCC_PLLCFGR_PLLN_MUL389_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL390				(RCC_PLLCFGR_PLLN_MUL390_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL391				(RCC_PLLCFGR_PLLN_MUL391_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL392				(RCC_PLLCFGR_PLLN_MUL392_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL393				(RCC_PLLCFGR_PLLN_MUL393_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL394				(RCC_PLLCFGR_PLLN_MUL394_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL395				(RCC_PLLCFGR_PLLN_MUL395_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL396				(RCC_PLLCFGR_PLLN_MUL396_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL397				(RCC_PLLCFGR_PLLN_MUL397_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL398				(RCC_PLLCFGR_PLLN_MUL398_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL399				(RCC_PLLCFGR_PLLN_MUL399_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL400				(RCC_PLLCFGR_PLLN_MUL400_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL401				(RCC_PLLCFGR_PLLN_MUL401_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL402				(RCC_PLLCFGR_PLLN_MUL402_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL403				(RCC_PLLCFGR_PLLN_MUL403_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL404				(RCC_PLLCFGR_PLLN_MUL404_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL405				(RCC_PLLCFGR_PLLN_MUL405_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL406				(RCC_PLLCFGR_PLLN_MUL406_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL407				(RCC_PLLCFGR_PLLN_MUL407_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL408				(RCC_PLLCFGR_PLLN_MUL408_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL409				(RCC_PLLCFGR_PLLN_MUL409_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL410				(RCC_PLLCFGR_PLLN_MUL410_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL411				(RCC_PLLCFGR_PLLN_MUL411_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL412				(RCC_PLLCFGR_PLLN_MUL412_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL413				(RCC_PLLCFGR_PLLN_MUL413_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL414				(RCC_PLLCFGR_PLLN_MUL414_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL415				(RCC_PLLCFGR_PLLN_MUL415_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL416				(RCC_PLLCFGR_PLLN_MUL416_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL417				(RCC_PLLCFGR_PLLN_MUL417_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL418				(RCC_PLLCFGR_PLLN_MUL418_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL419				(RCC_PLLCFGR_PLLN_MUL419_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL420				(RCC_PLLCFGR_PLLN_MUL420_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL421				(RCC_PLLCFGR_PLLN_MUL421_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL422				(RCC_PLLCFGR_PLLN_MUL422_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL423				(RCC_PLLCFGR_PLLN_MUL423_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL424				(RCC_PLLCFGR_PLLN_MUL424_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL425				(RCC_PLLCFGR_PLLN_MUL425_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL426				(RCC_PLLCFGR_PLLN_MUL426_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL427				(RCC_PLLCFGR_PLLN_MUL427_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL428				(RCC_PLLCFGR_PLLN_MUL428_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL429				(RCC_PLLCFGR_PLLN_MUL429_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL430				(RCC_PLLCFGR_PLLN_MUL430_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL431				(RCC_PLLCFGR_PLLN_MUL431_value << RCC_PLLCFGR_PLLN_bit)
#define RCC_PLLCFGR_PLLN_MUL432				(RCC_PLLCFGR_PLLN_MUL432_value << RCC_PLLCFGR_PLLN_bit)

#define RCC_PLLCFGR_PLLM_DIV2				(RCC_PLLCFGR_PLLM_DIV2_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV3				(RCC_PLLCFGR_PLLM_DIV3_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV4				(RCC_PLLCFGR_PLLM_DIV4_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV5				(RCC_PLLCFGR_PLLM_DIV5_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV6				(RCC_PLLCFGR_PLLM_DIV6_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV7				(RCC_PLLCFGR_PLLM_DIV7_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV8				(RCC_PLLCFGR_PLLM_DIV8_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV9				(RCC_PLLCFGR_PLLM_DIV9_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV10				(RCC_PLLCFGR_PLLM_DIV10_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV11				(RCC_PLLCFGR_PLLM_DIV11_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV12				(RCC_PLLCFGR_PLLM_DIV12_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV13				(RCC_PLLCFGR_PLLM_DIV13_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV14				(RCC_PLLCFGR_PLLM_DIV14_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV15				(RCC_PLLCFGR_PLLM_DIV15_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV16				(RCC_PLLCFGR_PLLM_DIV16_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV17				(RCC_PLLCFGR_PLLM_DIV17_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV18				(RCC_PLLCFGR_PLLM_DIV18_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV19				(RCC_PLLCFGR_PLLM_DIV19_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV20				(RCC_PLLCFGR_PLLM_DIV20_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV21				(RCC_PLLCFGR_PLLM_DIV21_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV22				(RCC_PLLCFGR_PLLM_DIV22_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV23				(RCC_PLLCFGR_PLLM_DIV23_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV24				(RCC_PLLCFGR_PLLM_DIV24_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV25				(RCC_PLLCFGR_PLLM_DIV25_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV26				(RCC_PLLCFGR_PLLM_DIV26_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV27				(RCC_PLLCFGR_PLLM_DIV27_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV28				(RCC_PLLCFGR_PLLM_DIV28_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV29				(RCC_PLLCFGR_PLLM_DIV29_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV30				(RCC_PLLCFGR_PLLM_DIV30_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV31				(RCC_PLLCFGR_PLLM_DIV31_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV32				(RCC_PLLCFGR_PLLM_DIV32_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV33				(RCC_PLLCFGR_PLLM_DIV33_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV34				(RCC_PLLCFGR_PLLM_DIV34_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV35				(RCC_PLLCFGR_PLLM_DIV35_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV36				(RCC_PLLCFGR_PLLM_DIV36_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV37				(RCC_PLLCFGR_PLLM_DIV37_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV38				(RCC_PLLCFGR_PLLM_DIV38_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV39				(RCC_PLLCFGR_PLLM_DIV39_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV40				(RCC_PLLCFGR_PLLM_DIV40_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV41				(RCC_PLLCFGR_PLLM_DIV41_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV42				(RCC_PLLCFGR_PLLM_DIV42_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV43				(RCC_PLLCFGR_PLLM_DIV43_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV44				(RCC_PLLCFGR_PLLM_DIV44_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV45				(RCC_PLLCFGR_PLLM_DIV45_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV46				(RCC_PLLCFGR_PLLM_DIV46_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV47				(RCC_PLLCFGR_PLLM_DIV47_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV48				(RCC_PLLCFGR_PLLM_DIV48_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV49				(RCC_PLLCFGR_PLLM_DIV49_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV50				(RCC_PLLCFGR_PLLM_DIV50_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV51				(RCC_PLLCFGR_PLLM_DIV51_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV52				(RCC_PLLCFGR_PLLM_DIV52_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV53				(RCC_PLLCFGR_PLLM_DIV53_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV54				(RCC_PLLCFGR_PLLM_DIV54_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV55				(RCC_PLLCFGR_PLLM_DIV55_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV56				(RCC_PLLCFGR_PLLM_DIV56_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV57				(RCC_PLLCFGR_PLLM_DIV57_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV58				(RCC_PLLCFGR_PLLM_DIV58_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV59				(RCC_PLLCFGR_PLLM_DIV59_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV60				(RCC_PLLCFGR_PLLM_DIV60_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV61				(RCC_PLLCFGR_PLLM_DIV61_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV62				(RCC_PLLCFGR_PLLM_DIV62_value << RCC_PLLCFGR_PLLM_bit)
#define RCC_PLLCFGR_PLLM_DIV63				(RCC_PLLCFGR_PLLM_DIV63_value << RCC_PLLCFGR_PLLM_bit)

#define RCC_PLLCFGR_PLLQ_0_bb				bitband_t m_BITBAND_PERIPH(&RCC->PLLCFGR, RCC_PLLCFGR_PLLQ_0_bit)
#define RCC_PLLCFGR_PLLQ_1_bb				bitband_t m_BITBAND_PERIPH(&RCC->PLLCFGR, RCC_PLLCFGR_PLLQ_1_bit)
#define RCC_PLLCFGR_PLLQ_2_bb				bitband_t m_BITBAND_PERIPH(&RCC->PLLCFGR, RCC_PLLCFGR_PLLQ_2_bit)
#define RCC_PLLCFGR_PLLQ_3_bb				bitband_t m_BITBAND_PERIPH(&RCC->PLLCFGR, RCC_PLLCFGR_PLLQ_3_bit)

#define RCC_PLLCFGR_PLLSRC_bb				bitband_t m_BITBAND_PERIPH(&RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC_bit)

#define RCC_PLLCFGR_PLLP_0_bb				bitband_t m_BITBAND_PERIPH(&RCC->PLLCFGR, RCC_PLLCFGR_PLLP_0_bit)
#define RCC_PLLCFGR_PLLP_1_bb				bitband_t m_BITBAND_PERIPH(&RCC->PLLCFGR, RCC_PLLCFGR_PLLP_1_bit)

#define RCC_PLLCFGR_PLLN_0_bb				bitband_t m_BITBAND_PERIPH(&RCC->PLLCFGR, RCC_PLLCFGR_PLLN_0_bit)
#define RCC_PLLCFGR_PLLN_1_bb				bitband_t m_BITBAND_PERIPH(&RCC->PLLCFGR, RCC_PLLCFGR_PLLN_1_bit)
#define RCC_PLLCFGR_PLLN_2_bb				bitband_t m_BITBAND_PERIPH(&RCC->PLLCFGR, RCC_PLLCFGR_PLLN_2_bit)
#define RCC_PLLCFGR_PLLN_3_bb				bitband_t m_BITBAND_PERIPH(&RCC->PLLCFGR, RCC_PLLCFGR_PLLN_3_bit)
#define RCC_PLLCFGR_PLLN_4_bb				bitband_t m_BITBAND_PERIPH(&RCC->PLLCFGR, RCC_PLLCFGR_PLLN_4_bit)
#define RCC_PLLCFGR_PLLN_5_bb				bitband_t m_BITBAND_PERIPH(&RCC->PLLCFGR, RCC_PLLCFGR_PLLN_5_bit)
#define RCC_PLLCFGR_PLLN_6_bb				bitband_t m_BITBAND_PERIPH(&RCC->PLLCFGR, RCC_PLLCFGR_PLLN_6_bit)
#define RCC_PLLCFGR_PLLN_7_bb				bitband_t m_BITBAND_PERIPH(&RCC->PLLCFGR, RCC_PLLCFGR_PLLN_7_bit)
#define RCC_PLLCFGR_PLLN_8_bb				bitband_t m_BITBAND_PERIPH(&RCC->PLLCFGR, RCC_PLLCFGR_PLLN_8_bit)

#define RCC_PLLCFGR_PLLM_0_bb				bitband_t m_BITBAND_PERIPH(&RCC->PLLCFGR, RCC_PLLCFGR_PLLM_0_bit)
#define RCC_PLLCFGR_PLLM_1_bb				bitband_t m_BITBAND_PERIPH(&RCC->PLLCFGR, RCC_PLLCFGR_PLLM_1_bit)
#define RCC_PLLCFGR_PLLM_2_bb				bitband_t m_BITBAND_PERIPH(&RCC->PLLCFGR, RCC_PLLCFGR_PLLM_2_bit)
#define RCC_PLLCFGR_PLLM_3_bb				bitband_t m_BITBAND_PERIPH(&RCC->PLLCFGR, RCC_PLLCFGR_PLLM_3_bit)
#define RCC_PLLCFGR_PLLM_4_bb				bitband_t m_BITBAND_PERIPH(&RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4_bit)
#define RCC_PLLCFGR_PLLM_5_bb				bitband_t m_BITBAND_PERIPH(&RCC->PLLCFGR, RCC_PLLCFGR_PLLM_5_bit)

/*
+-----------------------------------------------------------------------------+
| RCC_CFGR - Clock Configuration Register
+-----------------------------------------------------------------------------+
*/

#define RCC_CFGR_MCO2_bit					30
#define RCC_CFGR_MCO2_0_bit					30
#define RCC_CFGR_MCO2_1_bit					31

#define RCC_CFGR_MCO2PRE_bit				27
#define RCC_CFGR_MCO2PRE_0_bit				27
#define RCC_CFGR_MCO2PRE_1_bit				28
#define RCC_CFGR_MCO2PRE_2_bit				29

#define RCC_CFGR_MCO1PRE_bit				24
#define RCC_CFGR_MCO1PRE_0_bit				24
#define RCC_CFGR_MCO1PRE_1_bit				25
#define RCC_CFGR_MCO1PRE_2_bit				26

#define RCC_CFGR_I2SSRC_bit					23

#define RCC_CFGR_MCO1_bit					21
#define RCC_CFGR_MCO1_0_bit					21
#define RCC_CFGR_MCO1_1_bit					22

#define RCC_CFGR_RTCPRE_bit					16
#define RCC_CFGR_RTCPRE_0_bit				16
#define RCC_CFGR_RTCPRE_1_bit				17
#define RCC_CFGR_RTCPRE_2_bit				18
#define RCC_CFGR_RTCPRE_3_bit				19
#define RCC_CFGR_RTCPRE_4_bit				20

#define RCC_CFGR_PPRE2_bit					13
#define RCC_CFGR_PPRE2_0_bit				13
#define RCC_CFGR_PPRE2_1_bit				14
#define RCC_CFGR_PPRE2_2_bit				15

#define RCC_CFGR_PPRE1_bit					10
#define RCC_CFGR_PPRE1_0_bit				10
#define RCC_CFGR_PPRE1_1_bit				11
#define RCC_CFGR_PPRE1_2_bit				12

#define RCC_CFGR_HPRE_bit					4
#define RCC_CFGR_HPRE_0_bit					4
#define RCC_CFGR_HPRE_1_bit					5
#define RCC_CFGR_HPRE_2_bit					6
#define RCC_CFGR_HPRE_3_bit					7

#define RCC_CFGR_SWS_bit					2
#define RCC_CFGR_SWS_0_bit					2
#define RCC_CFGR_SWS_1_bit					3

#define RCC_CFGR_SW_bit						0
#define RCC_CFGR_SW_0_bit					0
#define RCC_CFGR_SW_1_bit					1

#define RCC_CFGR_MCO2_SYSCLK_value			0
#define RCC_CFGR_MCO2_PLLI2S_value			1
#define RCC_CFGR_MCO2_HSE_value				2
#define RCC_CFGR_MCO2_PLL_value				3
#define RCC_CFGR_MCO2_mask					3

#define RCC_CFGR_MCO2PRE_DIV1_value			0
#define RCC_CFGR_MCO2PRE_DIV2_value			4
#define RCC_CFGR_MCO2PRE_DIV3_value			5
#define RCC_CFGR_MCO2PRE_DIV4_value			6
#define RCC_CFGR_MCO2PRE_DIV5_value			7
#define RCC_CFGR_MCO2PRE_mask				7

#define RCC_CFGR_MCO1PRE_DIV1_value			0
#define RCC_CFGR_MCO1PRE_DIV2_value			4
#define RCC_CFGR_MCO1PRE_DIV3_value			5
#define RCC_CFGR_MCO1PRE_DIV4_value			6
#define RCC_CFGR_MCO1PRE_DIV5_value			7
#define RCC_CFGR_MCO1PRE_mask				7

#define RCC_CFGR_I2SSRC_PLLI2S_value		0
#define RCC_CFGR_I2SSRC_CKIN_value			1
#define RCC_CFGR_I2SSRC_mask				1

#define RCC_CFGR_MCO1_HSI_value				0
#define RCC_CFGR_MCO1_LSE_value				1
#define RCC_CFGR_MCO1_HSE_value				2
#define RCC_CFGR_MCO1_PLL_value				3
#define RCC_CFGR_MCO1_mask					3

#define RCC_CFGR_RTCPRE_NOCLK1_value		0
#define RCC_CFGR_RTCPRE_NOCLK2_value		1
#define RCC_CFGR_RTCPRE_DIV2_value			2
#define RCC_CFGR_RTCPRE_DIV3_value			3
#define RCC_CFGR_RTCPRE_DIV4_value			4
#define RCC_CFGR_RTCPRE_DIV5_value			5
#define RCC_CFGR_RTCPRE_DIV6_value			6
#define RCC_CFGR_RTCPRE_DIV7_value			7
#define RCC_CFGR_RTCPRE_DIV8_value			8
#define RCC_CFGR_RTCPRE_DIV9_value			9
#define RCC_CFGR_RTCPRE_DIV10_value			10
#define RCC_CFGR_RTCPRE_DIV11_value			11
#define RCC_CFGR_RTCPRE_DIV12_value			12
#define RCC_CFGR_RTCPRE_DIV13_value			13
#define RCC_CFGR_RTCPRE_DIV14_value			14
#define RCC_CFGR_RTCPRE_DIV15_value			15
#define RCC_CFGR_RTCPRE_DIV16_value			16
#define RCC_CFGR_RTCPRE_DIV17_value			17
#define RCC_CFGR_RTCPRE_DIV18_value			18
#define RCC_CFGR_RTCPRE_DIV19_value			19
#define RCC_CFGR_RTCPRE_DIV20_value			20
#define RCC_CFGR_RTCPRE_DIV21_value			21
#define RCC_CFGR_RTCPRE_DIV22_value			22
#define RCC_CFGR_RTCPRE_DIV23_value			23
#define RCC_CFGR_RTCPRE_DIV24_value			24
#define RCC_CFGR_RTCPRE_DIV25_value			25
#define RCC_CFGR_RTCPRE_DIV26_value			26
#define RCC_CFGR_RTCPRE_DIV27_value			27
#define RCC_CFGR_RTCPRE_DIV28_value			28
#define RCC_CFGR_RTCPRE_DIV29_value			29
#define RCC_CFGR_RTCPRE_DIV30_value			30
#define RCC_CFGR_RTCPRE_DIV31_value			31
#define RCC_CFGR_RTCPRE_mask				31

#define RCC_CFGR_PPRE2_DIV1_value			0
#define RCC_CFGR_PPRE2_DIV2_value			4
#define RCC_CFGR_PPRE2_DIV4_value			5
#define RCC_CFGR_PPRE2_DIV8_value			6
#define RCC_CFGR_PPRE2_DIV16_value			7
#define RCC_CFGR_PPRE2_mask					7

#define RCC_CFGR_PPRE1_DIV1_value			0
#define RCC_CFGR_PPRE1_DIV2_value			4
#define RCC_CFGR_PPRE1_DIV4_value			5
#define RCC_CFGR_PPRE1_DIV8_value			6
#define RCC_CFGR_PPRE1_DIV16_value			7
#define RCC_CFGR_PPRE1_mask					7

#define RCC_CFGR_HPRE_DIV1_value			0
#define RCC_CFGR_HPRE_DIV2_value			8
#define RCC_CFGR_HPRE_DIV4_value			9
#define RCC_CFGR_HPRE_DIV8_value			10
#define RCC_CFGR_HPRE_DIV16_value			11
#define RCC_CFGR_HPRE_DIV64_value			12
#define RCC_CFGR_HPRE_DIV128_value			13
#define RCC_CFGR_HPRE_DIV256_value			14
#define RCC_CFGR_HPRE_DIV512_value			15
#define RCC_CFGR_HPRE_mask					15

#define RCC_CFGR_SWS_HSI_value				0
#define RCC_CFGR_SWS_HSE_value				1
#define RCC_CFGR_SWS_PLL_value				2
#define RCC_CFGR_SWS_mask					3

#define RCC_CFGR_SW_HSI_value				0
#define RCC_CFGR_SW_HSE_value				1
#define RCC_CFGR_SW_PLL_value				2
#define RCC_CFGR_SW_mask					3

#define RCC_CFGR_MCO2_SYSCLK				(RCC_CFGR_MCO2_SYSCLK_value << RCC_CFGR_MCO2_bit)
#define RCC_CFGR_MCO2_PLLI2S				(RCC_CFGR_MCO2_PLLI2S_value << RCC_CFGR_MCO2_bit)
#define RCC_CFGR_MCO2_HSE					(RCC_CFGR_MCO2_HSE_value << RCC_CFGR_MCO2_bit)
#define RCC_CFGR_MCO2_PLL					(RCC_CFGR_MCO2_PLL_value << RCC_CFGR_MCO2_bit)

#define RCC_CFGR_MCO2PRE_DIV1				(RCC_CFGR_MCO2PRE_DIV1_value << RCC_CFGR_MCO2PRE_bit)
#define RCC_CFGR_MCO2PRE_DIV2				(RCC_CFGR_MCO2PRE_DIV2_value << RCC_CFGR_MCO2PRE_bit)
#define RCC_CFGR_MCO2PRE_DIV3				(RCC_CFGR_MCO2PRE_DIV3_value << RCC_CFGR_MCO2PRE_bit)
#define RCC_CFGR_MCO2PRE_DIV4				(RCC_CFGR_MCO2PRE_DIV4_value << RCC_CFGR_MCO2PRE_bit)
#define RCC_CFGR_MCO2PRE_DIV5				(RCC_CFGR_MCO2PRE_DIV5_value << RCC_CFGR_MCO2PRE_bit)

#define RCC_CFGR_MCO1PRE_DIV1				(RCC_CFGR_MCO1PRE_DIV1_value << RCC_CFGR_MCO1PRE_bit)
#define RCC_CFGR_MCO1PRE_DIV2				(RCC_CFGR_MCO1PRE_DIV2_value << RCC_CFGR_MCO1PRE_bit)
#define RCC_CFGR_MCO1PRE_DIV3				(RCC_CFGR_MCO1PRE_DIV3_value << RCC_CFGR_MCO1PRE_bit)
#define RCC_CFGR_MCO1PRE_DIV4				(RCC_CFGR_MCO1PRE_DIV4_value << RCC_CFGR_MCO1PRE_bit)
#define RCC_CFGR_MCO1PRE_DIV5				(RCC_CFGR_MCO1PRE_DIV5_value << RCC_CFGR_MCO1PRE_bit)

#define RCC_CFGR_I2SSRC_PLLI2S				(RCC_CFGR_I2SSRC_PLLI2S_value << RCC_CFGR_I2SSRC_bit)
#define RCC_CFGR_I2SSRC_CKIN				(RCC_CFGR_I2SSRC_CKIN_value << RCC_CFGR_I2SSRC_bit)

#define RCC_CFGR_MCO1_HSI					(RCC_CFGR_MCO1_HSI_value << RCC_CFGR_MCO1_bit)
#define RCC_CFGR_MCO1_LSE					(RCC_CFGR_MCO1_LSE_value << RCC_CFGR_MCO1_bit)
#define RCC_CFGR_MCO1_HSE					(RCC_CFGR_MCO1_HSE_value << RCC_CFGR_MCO1_bit)
#define RCC_CFGR_MCO1_PLL					(RCC_CFGR_MCO1_PLL_value << RCC_CFGR_MCO1_bit)

#define RCC_CFGR_RTCPRE_NOCLK1				(RCC_CFGR_RTCPRE_NOCLK1_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_NOCLK2				(RCC_CFGR_RTCPRE_NOCLK2_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV2				(RCC_CFGR_RTCPRE_DIV2_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV3				(RCC_CFGR_RTCPRE_DIV3_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV4				(RCC_CFGR_RTCPRE_DIV4_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV5				(RCC_CFGR_RTCPRE_DIV5_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV6				(RCC_CFGR_RTCPRE_DIV6_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV7				(RCC_CFGR_RTCPRE_DIV7_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV8				(RCC_CFGR_RTCPRE_DIV8_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV9				(RCC_CFGR_RTCPRE_DIV9_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV10				(RCC_CFGR_RTCPRE_DIV10_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV11				(RCC_CFGR_RTCPRE_DIV11_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV12				(RCC_CFGR_RTCPRE_DIV12_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV13				(RCC_CFGR_RTCPRE_DIV13_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV14				(RCC_CFGR_RTCPRE_DIV14_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV15				(RCC_CFGR_RTCPRE_DIV15_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV16				(RCC_CFGR_RTCPRE_DIV16_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV17				(RCC_CFGR_RTCPRE_DIV17_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV18				(RCC_CFGR_RTCPRE_DIV18_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV19				(RCC_CFGR_RTCPRE_DIV19_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV20				(RCC_CFGR_RTCPRE_DIV20_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV21				(RCC_CFGR_RTCPRE_DIV21_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV22				(RCC_CFGR_RTCPRE_DIV22_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV23				(RCC_CFGR_RTCPRE_DIV23_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV24				(RCC_CFGR_RTCPRE_DIV24_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV25				(RCC_CFGR_RTCPRE_DIV25_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV26				(RCC_CFGR_RTCPRE_DIV26_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV27				(RCC_CFGR_RTCPRE_DIV27_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV28				(RCC_CFGR_RTCPRE_DIV28_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV29				(RCC_CFGR_RTCPRE_DIV29_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV30				(RCC_CFGR_RTCPRE_DIV30_value << RCC_CFGR_RTCPRE_bit)
#define RCC_CFGR_RTCPRE_DIV31				(RCC_CFGR_RTCPRE_DIV31_value << RCC_CFGR_RTCPRE_bit)

#define RCC_CFGR_MCO2_0_bb					bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_MCO2_0_bit)
#define RCC_CFGR_MCO2_1_bb					bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_MCO2_1_bit)

#define RCC_CFGR_MCO2PRE_0_bb				bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_MCO2PRE_0_bit)
#define RCC_CFGR_MCO2PRE_1_bb				bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_MCO2PRE_1_bit)
#define RCC_CFGR_MCO2PRE_2_bb				bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_MCO2PRE_2_bit)

#define RCC_CFGR_MCO1PRE_0_bb				bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_MCO1PRE_0_bit)
#define RCC_CFGR_MCO1PRE_1_bb				bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_MCO1PRE_1_bit)
#define RCC_CFGR_MCO1PRE_2_bb				bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_MCO1PRE_2_bit)

#define RCC_CFGR_I2SSRC_bb					bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_I2SSRC_bit)

#define RCC_CFGR_MCO1_0_bb					bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_MCO1_0_bit)
#define RCC_CFGR_MCO1_1_bb					bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_MCO1_1_bit)

#define RCC_CFGR_RTCPRE_0_bb				bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_RTCPRE_0_bit)
#define RCC_CFGR_RTCPRE_1_bb				bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_RTCPRE_1_bit)
#define RCC_CFGR_RTCPRE_2_bb				bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_RTCPRE_2_bit)
#define RCC_CFGR_RTCPRE_3_bb				bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_RTCPRE_3_bit)
#define RCC_CFGR_RTCPRE_4_bb				bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_RTCPRE_4_bit)

#define RCC_CFGR_PPRE2_0_bb					bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_PPRE2_0_bit)
#define RCC_CFGR_PPRE2_1_bb					bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_PPRE2_1_bit)
#define RCC_CFGR_PPRE2_2_bb					bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_PPRE2_2_bit)

#define RCC_CFGR_PPRE1_0_bb					bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_PPRE1_0_bit)
#define RCC_CFGR_PPRE1_1_bb					bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_PPRE1_1_bit)
#define RCC_CFGR_PPRE1_2_bb					bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_PPRE1_2_bit)

#define RCC_CFGR_HPRE_0_bb					bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_HPRE_0_bit)
#define RCC_CFGR_HPRE_1_bb					bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_HPRE_1_bit)
#define RCC_CFGR_HPRE_2_bb					bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_HPRE_2_bit)
#define RCC_CFGR_HPRE_3_bb					bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_HPRE_3_bit)

#define RCC_CFGR_SWS_0_bb					bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_SWS_0_bit)
#define RCC_CFGR_SWS_1_bb					bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_SWS_1_bit)

#define RCC_CFGR_SW_0_bb					bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_SW_0_bit)
#define RCC_CFGR_SW_1_bb					bitband_t m_BITBAND_PERIPH(&RCC->CFGR, RCC_CFGR_SW_1_bit)

/*
+-----------------------------------------------------------------------------+
| RCC_CIR - Clock interrupt register
+-----------------------------------------------------------------------------+
*/

#define RCC_CIR_CSSC_bit					23
#define RCC_CIR_PLLI2SRDYC_bit				21
#define RCC_CIR_PLLRDYC_bit					20
#define RCC_CIR_HSERDYC_bit					19
#define RCC_CIR_HSIRDYC_bit					18
#define RCC_CIR_LSERDYC_bit					17
#define RCC_CIR_LSIRDYC_bit					16
#define RCC_CIR_PLLI2SRDYIE_bit				13
#define RCC_CIR_PLLRDYIE_bit				12
#define RCC_CIR_HSERDYIE_bit				11
#define RCC_CIR_HSIRDYIE_bit				10
#define RCC_CIR_LSERDYIE_bit				9
#define RCC_CIR_LSIRDYIE_bit				8
#define RCC_CIR_CSSF_bit					7
#define RCC_CIR_PLLI2SRDYF_bit				5
#define RCC_CIR_PLLRDYF_bit					4
#define RCC_CIR_HSERDYF_bit					3
#define RCC_CIR_HSIRDYF_bit					2
#define RCC_CIR_LSERDYF_bit					1
#define RCC_CIR_LSIRDYF_bit					0

#define RCC_CIR_CSSC_bb						bitband_t m_BITBAND_PERIPH(&RCC->CIR, RCC_CIR_CSSC_bit)
#define RCC_CIR_PLLI2SRDYC_bb				bitband_t m_BITBAND_PERIPH(&RCC->CIR, RCC_CIR_PLLI2SRDYC_bit)
#define RCC_CIR_PLLRDYC_bb					bitband_t m_BITBAND_PERIPH(&RCC->CIR, RCC_CIR_PLLRDYC_bit)
#define RCC_CIR_HSERDYC_bb					bitband_t m_BITBAND_PERIPH(&RCC->CIR, RCC_CIR_HSERDYC_bit)
#define RCC_CIR_HSIRDYC_bb					bitband_t m_BITBAND_PERIPH(&RCC->CIR, RCC_CIR_HSIRDYC_bit)
#define RCC_CIR_LSERDYC_bb					bitband_t m_BITBAND_PERIPH(&RCC->CIR, RCC_CIR_LSERDYC_bit)
#define RCC_CIR_LSIRDYC_bb					bitband_t m_BITBAND_PERIPH(&RCC->CIR, RCC_CIR_LSIRDYC_bit)
#define RCC_CIR_PLLI2SRDYIE_bb				bitband_t m_BITBAND_PERIPH(&RCC->CIR, RCC_CIR_PLLI2SRDYIE_bit)
#define RCC_CIR_PLLRDYIE_bb					bitband_t m_BITBAND_PERIPH(&RCC->CIR, RCC_CIR_PLLRDYIE_bit)
#define RCC_CIR_HSERDYIE_bb					bitband_t m_BITBAND_PERIPH(&RCC->CIR, RCC_CIR_HSERDYIE_bit)
#define RCC_CIR_HSIRDYIE_bb					bitband_t m_BITBAND_PERIPH(&RCC->CIR, RCC_CIR_HSIRDYIE_bit)
#define RCC_CIR_LSERDYIE_bb					bitband_t m_BITBAND_PERIPH(&RCC->CIR, RCC_CIR_LSERDYIE_bit)
#define RCC_CIR_LSIRDYIE_bb					bitband_t m_BITBAND_PERIPH(&RCC->CIR, RCC_CIR_LSIRDYIE_bit)
#define RCC_CIR_CSSF_bb						bitband_t m_BITBAND_PERIPH(&RCC->CIR, RCC_CIR_CSSF_bit)
#define RCC_CIR_PLLI2SRDYF_bb				bitband_t m_BITBAND_PERIPH(&RCC->CIR, RCC_CIR_PLLI2SRDYF_bit)
#define RCC_CIR_PLLRDYF_bb					bitband_t m_BITBAND_PERIPH(&RCC->CIR, RCC_CIR_PLLRDYF_bit)
#define RCC_CIR_HSERDYF_bb					bitband_t m_BITBAND_PERIPH(&RCC->CIR, RCC_CIR_HSERDYF_bit)
#define RCC_CIR_HSIRDYF_bb					bitband_t m_BITBAND_PERIPH(&RCC->CIR, RCC_CIR_HSIRDYF_bit)
#define RCC_CIR_LSERDYF_bb					bitband_t m_BITBAND_PERIPH(&RCC->CIR, RCC_CIR_LSERDYF_bit)
#define RCC_CIR_LSIRDYF_bb					bitband_t m_BITBAND_PERIPH(&RCC->CIR, RCC_CIR_LSIRDYF_bit)

/*
+-----------------------------------------------------------------------------+
| RCC_AHB1RSTR - RCC AHB1 peripheral reset register
+-----------------------------------------------------------------------------+
*/

#define RCC_AHB1RSTR_OTGHSRST_bit			29
#define RCC_AHB1RSTR_ETHMACRST_bit			25

#define RCC_AHB1RSTR_DMA2RST_bit			22
#define RCC_AHB1RSTR_DMA1RST_bit			21

#define RCC_AHB1RSTR_CRCRST_bit				12

#define RCC_AHB1RSTR_GPIOIRST_bit			8
#define RCC_AHB1RSTR_GPIOHRST_bit			7
#define RCC_AHB1RSTR_GPIOGRST_bit			6
#define RCC_AHB1RSTR_GPIOFRST_bit			5
#define RCC_AHB1RSTR_GPIOERST_bit			4
#define RCC_AHB1RSTR_GPIODRST_bit			3
#define RCC_AHB1RSTR_GPIOCRST_bit			2
#define RCC_AHB1RSTR_GPIOBRST_bit			1
#define RCC_AHB1RSTR_GPIOARST_bit			0

#define RCC_AHB1RSTR_OTGHSRST_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1RSTR, RCC_AHB1RSTR_OTGHSRST_bit)
#define RCC_AHB1RSTR_ETHMACRST_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1RSTR, RCC_AHB1RSTR_ETHMACRST_bit)

#define RCC_AHB1RSTR_DMA2RST_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST_bit)
#define RCC_AHB1RSTR_DMA1RST_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST_bit)

#define RCC_AHB1RSTR_CRCRST_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST_bit)

#define RCC_AHB1RSTR_GPIOIRST_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1RSTR, RCC_AHB1RSTR_GPIOIRST_bit)
#define RCC_AHB1RSTR_GPIOHRST_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1RSTR, RCC_AHB1RSTR_GPIOHRST_bit)
#define RCC_AHB1RSTR_GPIOGRST_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1RSTR, RCC_AHB1RSTR_GPIOGRST_bit)
#define RCC_AHB1RSTR_GPIOFRST_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1RSTR, RCC_AHB1RSTR_GPIOFRST_bit)
#define RCC_AHB1RSTR_GPIOERST_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1RSTR, RCC_AHB1RSTR_GPIOERST_bit)
#define RCC_AHB1RSTR_GPIODRST_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1RSTR, RCC_AHB1RSTR_GPIODRST_bit)
#define RCC_AHB1RSTR_GPIOCRST_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1RSTR, RCC_AHB1RSTR_GPIOCRST_bit)
#define RCC_AHB1RSTR_GPIOBRST_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1RSTR, RCC_AHB1RSTR_GPIOBRST_bit)
#define RCC_AHB1RSTR_GPIOARST_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1RSTR, RCC_AHB1RSTR_GPIOARST_bit)

/*
+-----------------------------------------------------------------------------+
| RCC_AHB2RSTR - RCC AHB2 peripheral reset register
+-----------------------------------------------------------------------------+
*/

#define RCC_AHB2RSTR_OTGFSRST_bit			7
#define RCC_AHB2RSTR_RNGRST_bit				6
#define RCC_AHB2RSTR_HASHRST_bit			5
#define RCC_AHB2RSTR_CRYPRST_bit			4
#define RCC_AHB2RSTR_DCMIRST_bit			0

#define RCC_AHB2RSTR_OTGFSRST_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST_bit)
#define RCC_AHB2RSTR_RNGRST_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST_bit)
#define RCC_AHB2RSTR_HASHRST_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST_bit)
#define RCC_AHB2RSTR_CRYPRST_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB2RSTR, RCC_AHB2RSTR_CRYPRST_bit)
#define RCC_AHB2RSTR_DCMIRST_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST_bit)

/*
+-----------------------------------------------------------------------------+
| RCC_AHB3RSTR - RCC AHB3 peripheral reset register
+-----------------------------------------------------------------------------+
*/

#define RCC_AHB3RSTR_FSMCRST_bit			0

#define RCC_AHB3RSTR_FSMCRST_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB3RSTR, RCC_AHB3RSTR_FSMCRST_bit)

/*
+-----------------------------------------------------------------------------+
| RCC_APB1RSTR - APB1 peripheral reset register
+-----------------------------------------------------------------------------+
*/

#define RCC_APB1RSTR_DACRST_bit				29
#define RCC_APB1RSTR_PWRRST_bit				28

#define RCC_APB1RSTR_CAN2RST_bit			26
#define RCC_APB1RSTR_CAN1RST_bit			25

#define RCC_APB1RSTR_I2C3RST_bit			23
#define RCC_APB1RSTR_I2C2RST_bit			22
#define RCC_APB1RSTR_I2C1RST_bit			21

#define RCC_APB1RSTR_UART5RST_bit			20
#define RCC_APB1RSTR_UART4RST_bit			19
#define RCC_APB1RSTR_USART3RST_bit			18
#define RCC_APB1RSTR_USART2RST_bit			17

#define RCC_APB1RSTR_SPI3RST_bit			15
#define RCC_APB1RSTR_SPI2RST_bit			14

#define RCC_APB1RSTR_WWDGRST_bit			11

#define RCC_APB1RSTR_TIM14RST_bit			8
#define RCC_APB1RSTR_TIM13RST_bit			7
#define RCC_APB1RSTR_TIM12RST_bit			6
#define RCC_APB1RSTR_TIM7RST_bit			5
#define RCC_APB1RSTR_TIM6RST_bit			4
#define RCC_APB1RSTR_TIM5RST_bit			3
#define RCC_APB1RSTR_TIM4RST_bit			2
#define RCC_APB1RSTR_TIM3RST_bit			1
#define RCC_APB1RSTR_TIM2RST_bit			0

#define RCC_APB1RSTR_DACRST_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1RSTR, RCC_APB1RSTR_DACRST_bit)
#define RCC_APB1RSTR_PWRRST_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1RSTR, RCC_APB1RSTR_PWRRST_bit)

#define RCC_APB1RSTR_CAN2RST_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1RSTR, RCC_APB1RSTR_CAN2RST_bit)
#define RCC_APB1RSTR_CAN1RST_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1RSTR, RCC_APB1RSTR_CAN1RST_bit)

#define RCC_APB1RSTR_I2C3RST_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1RSTR, RCC_APB1RSTR_I2C3RST_bit)
#define RCC_APB1RSTR_I2C2RST_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1RSTR, RCC_APB1RSTR_I2C2RST_bit)
#define RCC_APB1RSTR_I2C1RST_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1RSTR, RCC_APB1RSTR_I2C1RST_bit)

#define RCC_APB1RSTR_UART5RST_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1RSTR, RCC_APB1RSTR_UART5RST_bit)
#define RCC_APB1RSTR_UART4RST_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1RSTR, RCC_APB1RSTR_UART4RST_bit)
#define RCC_APB1RSTR_USART3RST_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1RSTR, RCC_APB1RSTR_USART3RST_bit)
#define RCC_APB1RSTR_USART2RST_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1RSTR, RCC_APB1RSTR_USART2RST_bit)

#define RCC_APB1RSTR_SPI3RST_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1RSTR, RCC_APB1RSTR_SPI3RST_bit)
#define RCC_APB1RSTR_SPI2RST_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1RSTR, RCC_APB1RSTR_SPI2RST_bit)

#define RCC_APB1RSTR_WWDGRST_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1RSTR, RCC_APB1RSTR_WWDGRST_bit)

#define RCC_APB1RSTR_TIM14RST_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1RSTR, RCC_APB1RSTR_TIM14RST_bit)
#define RCC_APB1RSTR_TIM13RST_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1RSTR, RCC_APB1RSTR_TIM13RST_bit)
#define RCC_APB1RSTR_TIM12RST_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1RSTR, RCC_APB1RSTR_TIM12RST_bit)
#define RCC_APB1RSTR_TIM7RST_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1RSTR, RCC_APB1RSTR_TIM7RST_bit)
#define RCC_APB1RSTR_TIM6RST_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1RSTR, RCC_APB1RSTR_TIM6RST_bit)
#define RCC_APB1RSTR_TIM5RST_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1RSTR, RCC_APB1RSTR_TIM5RST_bit)
#define RCC_APB1RSTR_TIM4RST_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1RSTR, RCC_APB1RSTR_TIM4RST_bit)
#define RCC_APB1RSTR_TIM3RST_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1RSTR, RCC_APB1RSTR_TIM3RST_bit)
#define RCC_APB1RSTR_TIM2RST_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1RSTR, RCC_APB1RSTR_TIM2RST_bit)

/*
+-----------------------------------------------------------------------------+
| RCC_APB2RSTR - APB2 peripheral reset register
+-----------------------------------------------------------------------------+
*/

#define RCC_APB2RSTR_TIM11RST_bit			18
#define RCC_APB2RSTR_TIM10RST_bit			17
#define RCC_APB2RSTR_TIM9RST_bit			16

#define RCC_APB2RSTR_SYSCFGRST_bit			14
#define RCC_APB2RSTR_SPI1RST_bit			12
#define RCC_APB2RSTR_SDIORST_bit			11
#define RCC_APB2RSTR_ADCRST_bit				8

#define RCC_APB2RSTR_USART6RST_bit			5
#define RCC_APB2RSTR_USART1RST_bit			4

#define RCC_APB2RSTR_TIM8RST_bit			1
#define RCC_APB2RSTR_TIM1RST_bit			0

#define RCC_APB2RSTR_TIM11RST_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB2RSTR, RCC_APB2RSTR_TIM11RST_bit)
#define RCC_APB2RSTR_TIM10RST_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB2RSTR, RCC_APB2RSTR_TIM10RST_bit)
#define RCC_APB2RSTR_TIM9RST_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB2RSTR, RCC_APB2RSTR_TIM9RST_bit)

#define RCC_APB2RSTR_SYSCFGRST_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST_bit)
#define RCC_APB2RSTR_SPI1RST_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST_bit)
#define RCC_APB2RSTR_SDIORST_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB2RSTR, RCC_APB2RSTR_SDIORST_bit)
#define RCC_APB2RSTR_ADCRST_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB2RSTR, RCC_APB2RSTR_ADCRST_bit)

#define RCC_APB2RSTR_USART6RST_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB2RSTR, RCC_APB2RSTR_USART6RST_bit)
#define RCC_APB2RSTR_USART1RST_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB2RSTR, RCC_APB2RSTR_USART1RST_bit)

#define RCC_APB2RSTR_TIM8RST_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST_bit)
#define RCC_APB2RSTR_TIM1RST_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST_bit)

/*
+-----------------------------------------------------------------------------+
| RCC_AHB1ENR - RCC AHB1 peripheral clock register
+-----------------------------------------------------------------------------+
*/

#define RCC_AHB1ENR_OTGHSULPIEN_bit			30
#define RCC_AHB1ENR_OTGHSEN_bit				29

#define RCC_AHB1ENR_ETHMACPTPEN_bit			28
#define RCC_AHB1ENR_ETHMACRXEN_bit			27
#define RCC_AHB1ENR_ETHMACTXEN_bit			26
#define RCC_AHB1ENR_ETHMACEN_bit			25

#define RCC_AHB1ENR_DMA2EN_bit				22
#define RCC_AHB1ENR_DMA1EN_bit				21

#define RCC_AHB1ENR_CCMDATARAMEN_bit		20
#define RCC_AHB1ENR_BKPSRAMEN_bit			18
#define RCC_AHB1ENR_CRCEN_bit				12

#define RCC_AHB1ENR_GPIOIEN_bit				8
#define RCC_AHB1ENR_GPIOHEN_bit				7
#define RCC_AHB1ENR_GPIOGEN_bit				6
#define RCC_AHB1ENR_GPIOFEN_bit				5
#define RCC_AHB1ENR_GPIOEEN_bit				4
#define RCC_AHB1ENR_GPIODEN_bit				3
#define RCC_AHB1ENR_GPIOCEN_bit				2
#define RCC_AHB1ENR_GPIOBEN_bit				1
#define RCC_AHB1ENR_GPIOAEN_bit				0

#define RCC_AHB1ENR_OTGHSULPIEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN_bit)
#define RCC_AHB1ENR_OTGHSEN_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN_bit)

#define RCC_AHB1ENR_ETHMACPTPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN_bit)
#define RCC_AHB1ENR_ETHMACRXEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN_bit)
#define RCC_AHB1ENR_ETHMACTXEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN_bit)
#define RCC_AHB1ENR_ETHMACEN_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN_bit)

#define RCC_AHB1ENR_DMA2EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN_bit)
#define RCC_AHB1ENR_DMA1EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN_bit)

#define RCC_AHB1ENR_CCMDATARAMEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN_bit)
#define RCC_AHB1ENR_BKPSRAMEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN_bit)
#define RCC_AHB1ENR_CRCEN_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB1ENR, RCC_AHB1ENR_CRCEN_bit)

#define RCC_AHB1ENR_GPIOIEN_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN_bit)
#define RCC_AHB1ENR_GPIOHEN_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN_bit)
#define RCC_AHB1ENR_GPIOGEN_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN_bit)
#define RCC_AHB1ENR_GPIOFEN_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN_bit)
#define RCC_AHB1ENR_GPIOEEN_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN_bit)
#define RCC_AHB1ENR_GPIODEN_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN_bit)
#define RCC_AHB1ENR_GPIOCEN_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN_bit)
#define RCC_AHB1ENR_GPIOBEN_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN_bit)
#define RCC_AHB1ENR_GPIOAEN_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN_bit)

/*
+-----------------------------------------------------------------------------+
| RCC_AHB2ENR - RCC AHB2 peripheral clock enable register
+-----------------------------------------------------------------------------+
*/

#define RCC_AHB2ENR_OTGFSEN_bit				7
#define RCC_AHB2ENR_RNGEN_bit				6
#define RCC_AHB2ENR_HASHEN_bit				5
#define RCC_AHB2ENR_CRYPEN_bit				4
#define RCC_AHB2ENR_DCMIEN_bit				0

#define RCC_AHB2ENR_OTGFSEN_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN_bit)
#define RCC_AHB2ENR_RNGEN_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB2ENR, RCC_AHB2ENR_RNGEN_bit)
#define RCC_AHB2ENR_HASHEN_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB2ENR, RCC_AHB2ENR_HASHEN_bit)
#define RCC_AHB2ENR_CRYPEN_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN_bit)
#define RCC_AHB2ENR_DCMIEN_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN_bit)

/*
+-----------------------------------------------------------------------------+
| RCC_AHB3ENR - RCC AHB3 peripheral clock enable register
+-----------------------------------------------------------------------------+
*/

#define RCC_AHB3ENR_FSMCEN_bit				0

#define RCC_AHB3ENR_FSMCEN_bb				bitband_t m_BITBAND_PERIPH(&RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN_bit)

/*
+-----------------------------------------------------------------------------+
| RCC_APB1ENR - RCC APB1 peripheral clock enable register
+-----------------------------------------------------------------------------+
*/

#define RCC_APB1ENR_DACEN_bit				29
#define RCC_APB1ENR_PWREN_bit				28

#define RCC_APB1ENR_CAN2EN_bit				26
#define RCC_APB1ENR_CAN1EN_bit				25

#define RCC_APB1ENR_I2C3EN_bit				23
#define RCC_APB1ENR_I2C2EN_bit				22
#define RCC_APB1ENR_I2C1EN_bit				21

#define RCC_APB1ENR_UART5EN_bit				20
#define RCC_APB1ENR_UART4EN_bit				19
#define RCC_APB1ENR_USART3EN_bit			18
#define RCC_APB1ENR_USART2EN_bit			17

#define RCC_APB1ENR_SPI3EN_bit				15
#define RCC_APB1ENR_SPI2EN_bit				14

#define RCC_APB1ENR_WWDGEN_bit				11

#define RCC_APB1ENR_TIM14EN_bit				8
#define RCC_APB1ENR_TIM13EN_bit				7
#define RCC_APB1ENR_TIM12EN_bit				6
#define RCC_APB1ENR_TIM7EN_bit				5
#define RCC_APB1ENR_TIM6EN_bit				4
#define RCC_APB1ENR_TIM5EN_bit				3
#define RCC_APB1ENR_TIM4EN_bit				2
#define RCC_APB1ENR_TIM3EN_bit				1
#define RCC_APB1ENR_TIM2EN_bit				0

#define RCC_APB1ENR_DACEN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1ENR, RCC_APB1ENR_DACEN_bit)
#define RCC_APB1ENR_PWREN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1ENR, RCC_APB1ENR_PWREN_bit)

#define RCC_APB1ENR_CAN2EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1ENR, RCC_APB1ENR_CAN2EN_bit)
#define RCC_APB1ENR_CAN1EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1ENR, RCC_APB1ENR_CAN1EN_bit)

#define RCC_APB1ENR_I2C3EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1ENR, RCC_APB1ENR_I2C3EN_bit)
#define RCC_APB1ENR_I2C2EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1ENR, RCC_APB1ENR_I2C2EN_bit)
#define RCC_APB1ENR_I2C1EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1ENR, RCC_APB1ENR_I2C1EN_bit)

#define RCC_APB1ENR_UART5EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1ENR, RCC_APB1ENR_UART5EN_bit)
#define RCC_APB1ENR_UART4EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1ENR, RCC_APB1ENR_UART4EN_bit)
#define RCC_APB1ENR_USART3EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1ENR, RCC_APB1ENR_USART3EN_bit)
#define RCC_APB1ENR_USART2EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1ENR, RCC_APB1ENR_USART2EN_bit)

#define RCC_APB1ENR_SPI3EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1ENR, RCC_APB1ENR_SPI3EN_bit)
#define RCC_APB1ENR_SPI2EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1ENR, RCC_APB1ENR_SPI2EN_bit)

#define RCC_APB1ENR_WWDGEN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1ENR, RCC_APB1ENR_WWDGEN_bit)

#define RCC_APB1ENR_TIM14EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1ENR, RCC_APB1ENR_TIM14EN_bit)
#define RCC_APB1ENR_TIM13EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1ENR, RCC_APB1ENR_TIM13EN_bit)
#define RCC_APB1ENR_TIM12EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1ENR, RCC_APB1ENR_TIM12EN_bit)
#define RCC_APB1ENR_TIM7EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1ENR, RCC_APB1ENR_TIM7EN_bit)
#define RCC_APB1ENR_TIM6EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1ENR, RCC_APB1ENR_TIM6EN_bit)
#define RCC_APB1ENR_TIM5EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1ENR, RCC_APB1ENR_TIM5EN_bit)
#define RCC_APB1ENR_TIM4EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1ENR, RCC_APB1ENR_TIM4EN_bit)
#define RCC_APB1ENR_TIM3EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1ENR, RCC_APB1ENR_TIM3EN_bit)
#define RCC_APB1ENR_TIM2EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB1ENR, RCC_APB1ENR_TIM2EN_bit)

/*
+-----------------------------------------------------------------------------+
| RCC_APB2ENR - RCC APB2 peripheral clock enable register
+-----------------------------------------------------------------------------+
*/

#define RCC_APB2ENR_TIM11EN_bit				18
#define RCC_APB2ENR_TIM10EN_bit				17
#define RCC_APB2ENR_TIM9EN_bit				16

#define RCC_APB2ENR_SYSCFGEN_bit			14
#define RCC_APB2ENR_SPI1EN_bit				12
#define RCC_APB2ENR_SDIOEN_bit				11

#define RCC_APB2ENR_ADC3EN_bit				10
#define RCC_APB2ENR_ADC2EN_bit				9
#define RCC_APB2ENR_ADC1EN_bit				8

#define RCC_APB2ENR_USART6EN_bit			5
#define RCC_APB2ENR_USART1EN_bit			4

#define RCC_APB2ENR_TIM8EN_bit				1
#define RCC_APB2ENR_TIM1EN_bit				0

#define RCC_APB2ENR_TIM11EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB2ENR, RCC_APB2ENR_TIM11EN_bit)
#define RCC_APB2ENR_TIM10EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB2ENR, RCC_APB2ENR_TIM10EN_bit)
#define RCC_APB2ENR_TIM9EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB2ENR, RCC_APB2ENR_TIM9EN_bit)

#define RCC_APB2ENR_SYSCFGEN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN_bit)
#define RCC_APB2ENR_SPI1EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB2ENR, RCC_APB2ENR_SPI1EN_bit)
#define RCC_APB2ENR_SDIOEN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB2ENR, RCC_APB2ENR_SDIOEN_bit)

#define RCC_APB2ENR_ADC3EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB2ENR, RCC_APB2ENR_ADC3EN_bit)
#define RCC_APB2ENR_ADC2EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB2ENR, RCC_APB2ENR_ADC2EN_bit)
#define RCC_APB2ENR_ADC1EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB2ENR, RCC_APB2ENR_ADC1EN_bit)

#define RCC_APB2ENR_USART6EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB2ENR, RCC_APB2ENR_USART6EN_bit)
#define RCC_APB2ENR_USART1EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB2ENR, RCC_APB2ENR_USART1EN_bit)

#define RCC_APB2ENR_TIM8EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB2ENR, RCC_APB2ENR_TIM8EN_bit)
#define RCC_APB2ENR_TIM1EN_bb				bitband_t m_BITBAND_PERIPH(&RCC->APB2ENR, RCC_APB2ENR_TIM1EN_bit)

/*
+-----------------------------------------------------------------------------+
| RCC_AHB1LPENR - RCC AHB1 peripheral clock enable in low power mode register
+-----------------------------------------------------------------------------+
*/

#define RCC_AHB1LPENR_OTGHSULPILPEN_bit		30
#define RCC_AHB1LPENR_OTGHSLPEN_bit			29

#define RCC_AHB1LPENR_ETHMACPTPLPEN_bit		28
#define RCC_AHB1LPENR_ETHMACRXLPEN_bit		27
#define RCC_AHB1LPENR_ETHMACTXLPEN_bit		26
#define RCC_AHB1LPENR_ETHMACLPEN_bit		25

#define RCC_AHB1LPENR_DMA2LPEN_bit			22
#define RCC_AHB1LPENR_DMA1LPEN_bit			21

#define RCC_AHB1LPENR_BKPSRAMLPEN_bit		18

#define RCC_AHB1LPENR_SRAM2LPEN_bit			17
#define RCC_AHB1LPENR_SRAM1LPEN_bit			16

#define RCC_AHB1LPENR_FLITFLPEN_bit			15
#define RCC_AHB1LPENR_CRCLPEN_bit			12

#define RCC_AHB1LPENR_GPIOILPEN_bit			8
#define RCC_AHB1LPENR_GPIOHLPEN_bit			7
#define RCC_AHB1LPENR_GPIOGLPEN_bit			6
#define RCC_AHB1LPENR_GPIOFLPEN_bit			5
#define RCC_AHB1LPENR_GPIOELPEN_bit			4
#define RCC_AHB1LPENR_GPIODLPEN_bit			3
#define RCC_AHB1LPENR_GPIOCLPEN_bit			2
#define RCC_AHB1LPENR_GPIOBLPEN_bit			1
#define RCC_AHB1LPENR_GPIOALPEN_bit			0

#define RCC_AHB1LPENR_OTGHSULPILPEN_bb		bitband_t m_BITBAND_PERIPH(&RCC->AHB1LPENR, RCC_AHB1LPENR_OTGHSULPILPEN_bit)
#define RCC_AHB1LPENR_OTGHSLPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1LPENR, RCC_AHB1LPENR_OTGHSLPEN_bit)

#define RCC_AHB1LPENR_ETHMACPTPLPEN_bb		bitband_t m_BITBAND_PERIPH(&RCC->AHB1LPENR, RCC_AHB1LPENR_ETHMACPTPLPEN_bit)
#define RCC_AHB1LPENR_ETHMACRXLPEN_bb		bitband_t m_BITBAND_PERIPH(&RCC->AHB1LPENR, RCC_AHB1LPENR_ETHMACRXLPEN_bit)
#define RCC_AHB1LPENR_ETHMACTXLPEN_bb		bitband_t m_BITBAND_PERIPH(&RCC->AHB1LPENR, RCC_AHB1LPENR_ETHMACTXLPEN_bit)
#define RCC_AHB1LPENR_ETHMACLPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1LPENR, RCC_AHB1LPENR_ETHMACLPEN_bit)

#define RCC_AHB1LPENR_DMA2LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1LPENR, RCC_AHB1LPENR_DMA2LPEN_bit)
#define RCC_AHB1LPENR_DMA1LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1LPENR, RCC_AHB1LPENR_DMA1LPEN_bit)

#define RCC_AHB1LPENR_BKPSRAMLPEN_bb		bitband_t m_BITBAND_PERIPH(&RCC->AHB1LPENR, RCC_AHB1LPENR_BKPSRAMLPEN_bit)

#define RCC_AHB1LPENR_SRAM2LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1LPENR, RCC_AHB1LPENR_SRAM2LPEN_bit)
#define RCC_AHB1LPENR_SRAM1LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1LPENR, RCC_AHB1LPENR_SRAM1LPEN_bit)

#define RCC_AHB1LPENR_FLITFLPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1LPENR, RCC_AHB1LPENR_FLITFLPEN_bit)
#define RCC_AHB1LPENR_CRCLPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1LPENR, RCC_AHB1LPENR_CRCLPEN_bit)

#define RCC_AHB1LPENR_GPIOILPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1LPENR, RCC_AHB1LPENR_GPIOILPEN_bit)
#define RCC_AHB1LPENR_GPIOHLPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1LPENR, RCC_AHB1LPENR_GPIOHLPEN_bit)
#define RCC_AHB1LPENR_GPIOGLPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1LPENR, RCC_AHB1LPENR_GPIOGLPEN_bit)
#define RCC_AHB1LPENR_GPIOFLPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1LPENR, RCC_AHB1LPENR_GPIOFLPEN_bit)
#define RCC_AHB1LPENR_GPIOELPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1LPENR, RCC_AHB1LPENR_GPIOELPEN_bit)
#define RCC_AHB1LPENR_GPIODLPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1LPENR, RCC_AHB1LPENR_GPIODLPEN_bit)
#define RCC_AHB1LPENR_GPIOCLPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1LPENR, RCC_AHB1LPENR_GPIOCLPEN_bit)
#define RCC_AHB1LPENR_GPIOBLPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1LPENR, RCC_AHB1LPENR_GPIOBLPEN_bit)
#define RCC_AHB1LPENR_GPIOALPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB1LPENR, RCC_AHB1LPENR_GPIOALPEN_bit)

/*
+-----------------------------------------------------------------------------+
| RCC_AHB2LPENR - RCC AHB2 peripheral clock enable in low power mode register
+-----------------------------------------------------------------------------+
*/

#define RCC_AHB2LPENR_OTGFSLPEN_bit			7
#define RCC_AHB2LPENR_RNGLPEN_bit			6
#define RCC_AHB2LPENR_HASHLPEN_bit			5
#define RCC_AHB2LPENR_CRYPLPEN_bit			4
#define RCC_AHB2LPENR_DCMILPEN_bit			0

#define RCC_AHB2LPENR_OTGFSLPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB2LPENR, RCC_AHB2LPENR_OTGFSLPEN_bit)
#define RCC_AHB2LPENR_RNGLPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB2LPENR, RCC_AHB2LPENR_RNGLPEN_bit)
#define RCC_AHB2LPENR_HASHLPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB2LPENR, RCC_AHB2LPENR_HASHLPEN_bit)
#define RCC_AHB2LPENR_CRYPLPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB2LPENR, RCC_AHB2LPENR_CRYPLPEN_bit)
#define RCC_AHB2LPENR_DCMILPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB2LPENR, RCC_AHB2LPENR_DCMILPEN_bit)

/*
+-----------------------------------------------------------------------------+
| RCC_AHB3LPENR - RCC AHB3 peripheral clock enable register
+-----------------------------------------------------------------------------+
*/

#define RCC_AHB3LPENR_FSMCLPEN_bit			0

#define RCC_AHB3LPENR_FSMCLPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->AHB3LPENR, RCC_AHB3LPENR_FSMCLPEN_bit)

/*
+-----------------------------------------------------------------------------+
| RCC_APB1LPENR - RCC APB1 peripheral clock enable in low power mode register
+-----------------------------------------------------------------------------+
*/

#define RCC_APB1LPENR_DACLPEN_bit			29
#define RCC_APB1LPENR_PWRLPEN_bit			28

#define RCC_APB1LPENR_CAN2LPEN_bit			26
#define RCC_APB1LPENR_CAN1LPEN_bit			25

#define RCC_APB1LPENR_I2C3LPEN_bit			23
#define RCC_APB1LPENR_I2C2LPEN_bit			22
#define RCC_APB1LPENR_I2C1LPEN_bit			21

#define RCC_APB1LPENR_UART5LPEN_bit			20
#define RCC_APB1LPENR_UART4LPEN_bit			19
#define RCC_APB1LPENR_USART3LPEN_bit		18
#define RCC_APB1LPENR_USART2LPEN_bit		17

#define RCC_APB1LPENR_SPI3LPEN_bit			15
#define RCC_APB1LPENR_SPI2LPEN_bit			14

#define RCC_APB1LPENR_WWDGLPEN_bit			11

#define RCC_APB1LPENR_TIM14LPEN_bit			8
#define RCC_APB1LPENR_TIM13LPEN_bit			7
#define RCC_APB1LPENR_TIM12LPEN_bit			6
#define RCC_APB1LPENR_TIM7LPEN_bit			5
#define RCC_APB1LPENR_TIM6LPEN_bit			4
#define RCC_APB1LPENR_TIM5LPEN_bit			3
#define RCC_APB1LPENR_TIM4LPEN_bit			2
#define RCC_APB1LPENR_TIM3LPEN_bit			1
#define RCC_APB1LPENR_TIM2LPEN_bit			0

#define RCC_APB1LPENR_DACLPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1LPENR, RCC_APB1LPENR_DACLPEN_bit)
#define RCC_APB1LPENR_PWRLPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1LPENR, RCC_APB1LPENR_PWRLPEN_bit)

#define RCC_APB1LPENR_CAN2LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1LPENR, RCC_APB1LPENR_CAN2LPEN_bit)
#define RCC_APB1LPENR_CAN1LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1LPENR, RCC_APB1LPENR_CAN1LPEN_bit)

#define RCC_APB1LPENR_I2C3LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1LPENR, RCC_APB1LPENR_I2C3LPEN_bit)
#define RCC_APB1LPENR_I2C2LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1LPENR, RCC_APB1LPENR_I2C2LPEN_bit)
#define RCC_APB1LPENR_I2C1LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1LPENR, RCC_APB1LPENR_I2C1LPEN_bit)

#define RCC_APB1LPENR_UART5LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1LPENR, RCC_APB1LPENR_UART5LPEN_bit)
#define RCC_APB1LPENR_UART4LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1LPENR, RCC_APB1LPENR_UART4LPEN_bit)
#define RCC_APB1LPENR_USART3LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1LPENR, RCC_APB1LPENR_USART3LPEN_bit)
#define RCC_APB1LPENR_USART2LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1LPENR, RCC_APB1LPENR_USART2LPEN_bit)

#define RCC_APB1LPENR_SPI3LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1LPENR, RCC_APB1LPENR_SPI3LPEN_bit)
#define RCC_APB1LPENR_SPI2LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1LPENR, RCC_APB1LPENR_SPI2LPEN_bit)

#define RCC_APB1LPENR_WWDGLPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1LPENR, RCC_APB1LPENR_WWDGLPEN_bit)

#define RCC_APB1LPENR_TIM14LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1LPENR, RCC_APB1LPENR_TIM14LPEN_bit)
#define RCC_APB1LPENR_TIM13LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1LPENR, RCC_APB1LPENR_TIM13LPEN_bit)
#define RCC_APB1LPENR_TIM12LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1LPENR, RCC_APB1LPENR_TIM12LPEN_bit)
#define RCC_APB1LPENR_TIM7LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1LPENR, RCC_APB1LPENR_TIM7LPEN_bit)
#define RCC_APB1LPENR_TIM6LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1LPENR, RCC_APB1LPENR_TIM6LPEN_bit)
#define RCC_APB1LPENR_TIM5LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1LPENR, RCC_APB1LPENR_TIM5LPEN_bit)
#define RCC_APB1LPENR_TIM4LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1LPENR, RCC_APB1LPENR_TIM4LPEN_bit)
#define RCC_APB1LPENR_TIM3LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1LPENR, RCC_APB1LPENR_TIM3LPEN_bit)
#define RCC_APB1LPENR_TIM2LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB1LPENR, RCC_APB1LPENR_TIM2LPEN_bit)

/*
+-----------------------------------------------------------------------------+
| RCC_APB2LPENR - RCC APB2 peripheral clock enable register
+-----------------------------------------------------------------------------+
*/

#define RCC_APB2LPENR_TIM11LPEN_bit			18
#define RCC_APB2LPENR_TIM10LPEN_bit			17
#define RCC_APB2LPENR_TIM9LPEN_bit			16

#define RCC_APB2LPENR_SYSCFGLPEN_bit		14
#define RCC_APB2LPENR_SPI1LPEN_bit			12
#define RCC_APB2LPENR_SDIOLPEN_bit			11

#define RCC_APB2LPENR_ADC3LPEN_bit			10
#define RCC_APB2LPENR_ADC2LPEN_bit			9
#define RCC_APB2LPENR_ADC1LPEN_bit			8

#define RCC_APB2LPENR_USART6LPEN_bit		5
#define RCC_APB2LPENR_USART1LPEN_bit		4

#define RCC_APB2LPENR_TIM8LPEN_bit			1
#define RCC_APB2LPENR_TIM1LPEN_bit			0

#define RCC_APB2LPENR_TIM11LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB2LPENR, RCC_APB2LPENR_TIM11LPEN_bit)
#define RCC_APB2LPENR_TIM10LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB2LPENR, RCC_APB2LPENR_TIM10LPEN_bit)
#define RCC_APB2LPENR_TIM9LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB2LPENR, RCC_APB2LPENR_TIM9LPEN_bit)

#define RCC_APB2LPENR_SYSCFGLPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB2LPENR, RCC_APB2LPENR_SYSCFGLPEN_bit)
#define RCC_APB2LPENR_SPI1LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB2LPENR, RCC_APB2LPENR_SPI1LPEN_bit)
#define RCC_APB2LPENR_SDIOLPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB2LPENR, RCC_APB2LPENR_SDIOLPEN_bit)

#define RCC_APB2LPENR_ADC3LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB2LPENR, RCC_APB2LPENR_ADC3LPEN_bit)
#define RCC_APB2LPENR_ADC2LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB2LPENR, RCC_APB2LPENR_ADC2LPEN_bit)
#define RCC_APB2LPENR_ADC1LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB2LPENR, RCC_APB2LPENR_ADC1LPEN_bit)

#define RCC_APB2LPENR_USART6LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB2LPENR, RCC_APB2LPENR_USART6LPEN_bit)
#define RCC_APB2LPENR_USART1LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB2LPENR, RCC_APB2LPENR_USART1LPEN_bit)

#define RCC_APB2LPENR_TIM8LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB2LPENR, RCC_APB2LPENR_TIM8LPEN_bit)
#define RCC_APB2LPENR_TIM1LPEN_bb			bitband_t m_BITBAND_PERIPH(&RCC->APB2LPENR, RCC_APB2LPENR_TIM1LPEN_bit)

/*
+-----------------------------------------------------------------------------+
| RCC_BDCR - Backup domain control register
+-----------------------------------------------------------------------------+
*/

#define RCC_BDCR_BDRST_bit					16
#define RCC_BDCR_RTCEN_bit					15

#define RCC_BDCR_RTCSEL_bit					8
#define RCC_BDCR_RTCSEL_0_bit				8
#define RCC_BDCR_RTCSEL_1_bit				9

#define RCC_BDCR_LSEBYP_bit					2
#define RCC_BDCR_LSERDY_bit					1
#define RCC_BDCR_LSEON_bit					0

#define RCC_BDCR_RTCSEL_NOCLOCK_value		0
#define RCC_BDCR_RTCSEL_LSE_value			1
#define RCC_BDCR_RTCSEL_LSI_value			2
#define RCC_BDCR_RTCSEL_HSE_value			3
#define RCC_BDCR_RTCSEL_mask				3

#define RCC_BDCR_BDRST_bb					bitband_t m_BITBAND_PERIPH(&RCC->BDCR, RCC_BDCR_BDRST_bit)
#define RCC_BDCR_RTCEN_bb					bitband_t m_BITBAND_PERIPH(&RCC->BDCR, RCC_BDCR_RTCEN_bit)
#define RCC_BDCR_RTCSEL_0_bb				bitband_t m_BITBAND_PERIPH(&RCC->BDCR, RCC_BDCR_RTCSEL_0_bit)
#define RCC_BDCR_RTCSEL_1_bb				bitband_t m_BITBAND_PERIPH(&RCC->BDCR, RCC_BDCR_RTCSEL_1_bit)
#define RCC_BDCR_LSEBYP_bb					bitband_t m_BITBAND_PERIPH(&RCC->BDCR, RCC_BDCR_LSEBYP_bit)
#define RCC_BDCR_LSERDY_bb					bitband_t m_BITBAND_PERIPH(&RCC->BDCR, RCC_BDCR_LSERDY_bit)
#define RCC_BDCR_LSEON_bb					bitband_t m_BITBAND_PERIPH(&RCC->BDCR, RCC_BDCR_LSEON_bit)

/*
+-----------------------------------------------------------------------------+
| RCC_CSR - Control/status register
+-----------------------------------------------------------------------------+
*/

#define RCC_CSR_LPWRRSTF_bit				31
#define RCC_CSR_WWDGRSTF_bit				30
#define RCC_CSR_IWDGRSTF_bit				29
#define RCC_CSR_SFTRSTF_bit					28
#define RCC_CSR_PORRSTF_bit					27
#define RCC_CSR_PINRSTF_bit					26
#define RCC_CSR_BORRSTF_bit					25
#define RCC_CSR_RMVF_bit					24

#define RCC_CSR_LSIRDY_bit					1
#define RCC_CSR_LSION_bit					0

#define RCC_CSR_LPWRRSTF_bb					bitband_t m_BITBAND_PERIPH(&RCC->CSR, RCC_CSR_LPWRRSTF_bit)
#define RCC_CSR_WWDGRSTF_bb					bitband_t m_BITBAND_PERIPH(&RCC->CSR, RCC_CSR_WWDGRSTF_bit)
#define RCC_CSR_IWDGRSTF_bb					bitband_t m_BITBAND_PERIPH(&RCC->CSR, RCC_CSR_IWDGRSTF_bit)
#define RCC_CSR_SFTRSTF_bb					bitband_t m_BITBAND_PERIPH(&RCC->CSR, RCC_CSR_SFTRSTF_bit)
#define RCC_CSR_PORRSTF_bb					bitband_t m_BITBAND_PERIPH(&RCC->CSR, RCC_CSR_PORRSTF_bit)
#define RCC_CSR_PINRSTF_bb					bitband_t m_BITBAND_PERIPH(&RCC->CSR, RCC_CSR_PINRSTF_bit)
#define RCC_CSR_BORRSTF_bb					bitband_t m_BITBAND_PERIPH(&RCC->CSR, RCC_CSR_BORRSTF_bit)
#define RCC_CSR_RMVF_bb						bitband_t m_BITBAND_PERIPH(&RCC->CSR, RCC_CSR_RMVF_bit)

#define RCC_CSR_LSIRDY_bb					bitband_t m_BITBAND_PERIPH(&RCC->CSR, RCC_CSR_LSIRDY_bit)
#define RCC_CSR_LSION_bb					bitband_t m_BITBAND_PERIPH(&RCC->CSR, RCC_CSR_LSION_bit)

/*
+-----------------------------------------------------------------------------+
| RCC_SSCGR - RCC spread spectrum clock generation register
+-----------------------------------------------------------------------------+
*/

#define RCC_SSCGR_SSCGEN_bit				31
#define RCC_SSCGR_SPREADSEL_bit				30

#define RCC_SSCGR_INCSTEP_bit				13
#define RCC_SSCGR_INCSTEP_0_bit				13
#define RCC_SSCGR_INCSTEP_1_bit				14
#define RCC_SSCGR_INCSTEP_2_bit				15
#define RCC_SSCGR_INCSTEP_3_bit				16
#define RCC_SSCGR_INCSTEP_4_bit				17
#define RCC_SSCGR_INCSTEP_5_bit				18
#define RCC_SSCGR_INCSTEP_6_bit				19
#define RCC_SSCGR_INCSTEP_7_bit				20
#define RCC_SSCGR_INCSTEP_8_bit				21
#define RCC_SSCGR_INCSTEP_9_bit				22
#define RCC_SSCGR_INCSTEP_10_bit			23
#define RCC_SSCGR_INCSTEP_11_bit			24
#define RCC_SSCGR_INCSTEP_12_bit			25
#define RCC_SSCGR_INCSTEP_13_bit			26
#define RCC_SSCGR_INCSTEP_14_bit			27

#define RCC_SSCGR_MODPER_bit				0
#define RCC_SSCGR_MODPER_0_bit				0
#define RCC_SSCGR_MODPER_1_bit				1
#define RCC_SSCGR_MODPER_2_bit				2
#define RCC_SSCGR_MODPER_3_bit				3
#define RCC_SSCGR_MODPER_4_bit				4
#define RCC_SSCGR_MODPER_5_bit				5
#define RCC_SSCGR_MODPER_6_bit				6
#define RCC_SSCGR_MODPER_7_bit				7
#define RCC_SSCGR_MODPER_8_bit				8
#define RCC_SSCGR_MODPER_9_bit				9
#define RCC_SSCGR_MODPER_10_bit				10
#define RCC_SSCGR_MODPER_11_bit				11
#define RCC_SSCGR_MODPER_12_bit				12

#define RCC_SSCGR_SSCGEN_bb					bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_SSCGEN_bit)
#define RCC_SSCGR_SPREADSEL_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_SPREADSEL_bit)

#define RCC_SSCGR_INCSTEP_0_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_INCSTEP_0_bit)
#define RCC_SSCGR_INCSTEP_1_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_INCSTEP_1_bit)
#define RCC_SSCGR_INCSTEP_2_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_INCSTEP_2_bit)
#define RCC_SSCGR_INCSTEP_3_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_INCSTEP_3_bit)
#define RCC_SSCGR_INCSTEP_4_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_INCSTEP_4_bit)
#define RCC_SSCGR_INCSTEP_5_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_INCSTEP_5_bit)
#define RCC_SSCGR_INCSTEP_6_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_INCSTEP_6_bit)
#define RCC_SSCGR_INCSTEP_7_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_INCSTEP_7_bit)
#define RCC_SSCGR_INCSTEP_8_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_INCSTEP_8_bit)
#define RCC_SSCGR_INCSTEP_9_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_INCSTEP_9_bit)
#define RCC_SSCGR_INCSTEP_10_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_INCSTEP_10_bit)
#define RCC_SSCGR_INCSTEP_11_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_INCSTEP_11_bit)
#define RCC_SSCGR_INCSTEP_12_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_INCSTEP_12_bit)
#define RCC_SSCGR_INCSTEP_13_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_INCSTEP_13_bit)
#define RCC_SSCGR_INCSTEP_14_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_INCSTEP_14_bit)

#define RCC_SSCGR_MODPER_0_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_MODPER_0_bit)
#define RCC_SSCGR_MODPER_1_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_MODPER_1_bit)
#define RCC_SSCGR_MODPER_2_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_MODPER_2_bit)
#define RCC_SSCGR_MODPER_3_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_MODPER_3_bit)
#define RCC_SSCGR_MODPER_4_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_MODPER_4_bit)
#define RCC_SSCGR_MODPER_5_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_MODPER_5_bit)
#define RCC_SSCGR_MODPER_6_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_MODPER_6_bit)
#define RCC_SSCGR_MODPER_7_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_MODPER_7_bit)
#define RCC_SSCGR_MODPER_8_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_MODPER_8_bit)
#define RCC_SSCGR_MODPER_9_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_MODPER_9_bit)
#define RCC_SSCGR_MODPER_10_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_MODPER_10_bit)
#define RCC_SSCGR_MODPER_11_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_MODPER_11_bit)
#define RCC_SSCGR_MODPER_12_bb				bitband_t m_BITBAND_PERIPH(&RCC->SSCGR, RCC_SSCGR_MODPER_12_bit)

/*
+-----------------------------------------------------------------------------+
| RCC_PLLI2SCFGR - RCC PLLI2S configuration register
+-----------------------------------------------------------------------------+
*/

#define RCC_PLLI2SCFGR_PLLI2SR_bit			28
#define RCC_PLLI2SCFGR_PLLI2SR_0_bit		28
#define RCC_PLLI2SCFGR_PLLI2SR_1_bit		29
#define RCC_PLLI2SCFGR_PLLI2SR_2_bit		30

#define RCC_PLLI2SCFGR_PLLI2SN_bit			6
#define RCC_PLLI2SCFGR_PLLI2SN_0_bit		6
#define RCC_PLLI2SCFGR_PLLI2SN_1_bit		7
#define RCC_PLLI2SCFGR_PLLI2SN_2_bit		8
#define RCC_PLLI2SCFGR_PLLI2SN_3_bit		9
#define RCC_PLLI2SCFGR_PLLI2SN_4_bit		10
#define RCC_PLLI2SCFGR_PLLI2SN_5_bit		11
#define RCC_PLLI2SCFGR_PLLI2SN_6_bit		12
#define RCC_PLLI2SCFGR_PLLI2SN_7_bit		13
#define RCC_PLLI2SCFGR_PLLI2SN_8_bit		14

#define RCC_PLLI2SCFGR_PLLI2SR_DIV2_value	2
#define RCC_PLLI2SCFGR_PLLI2SR_DIV3_value	3
#define RCC_PLLI2SCFGR_PLLI2SR_DIV4_value	4
#define RCC_PLLI2SCFGR_PLLI2SR_DIV5_value	5
#define RCC_PLLI2SCFGR_PLLI2SR_DIV6_value	6
#define RCC_PLLI2SCFGR_PLLI2SR_DIV7_value	7
#define RCC_PLLI2SCFGR_PLLI2SR_mask			7

#define RCC_PLLI2SCFGR_PLLI2SN_MUL192_value		192
#define RCC_PLLI2SCFGR_PLLI2SN_MUL193_value		193
#define RCC_PLLI2SCFGR_PLLI2SN_MUL194_value		194
#define RCC_PLLI2SCFGR_PLLI2SN_MUL195_value		195
#define RCC_PLLI2SCFGR_PLLI2SN_MUL196_value		196
#define RCC_PLLI2SCFGR_PLLI2SN_MUL197_value		197
#define RCC_PLLI2SCFGR_PLLI2SN_MUL198_value		198
#define RCC_PLLI2SCFGR_PLLI2SN_MUL199_value		199
#define RCC_PLLI2SCFGR_PLLI2SN_MUL200_value		200
#define RCC_PLLI2SCFGR_PLLI2SN_MUL201_value		201
#define RCC_PLLI2SCFGR_PLLI2SN_MUL202_value		202
#define RCC_PLLI2SCFGR_PLLI2SN_MUL203_value		203
#define RCC_PLLI2SCFGR_PLLI2SN_MUL204_value		204
#define RCC_PLLI2SCFGR_PLLI2SN_MUL205_value		205
#define RCC_PLLI2SCFGR_PLLI2SN_MUL206_value		206
#define RCC_PLLI2SCFGR_PLLI2SN_MUL207_value		207
#define RCC_PLLI2SCFGR_PLLI2SN_MUL208_value		208
#define RCC_PLLI2SCFGR_PLLI2SN_MUL209_value		209
#define RCC_PLLI2SCFGR_PLLI2SN_MUL210_value		210
#define RCC_PLLI2SCFGR_PLLI2SN_MUL211_value		211
#define RCC_PLLI2SCFGR_PLLI2SN_MUL212_value		212
#define RCC_PLLI2SCFGR_PLLI2SN_MUL213_value		213
#define RCC_PLLI2SCFGR_PLLI2SN_MUL214_value		214
#define RCC_PLLI2SCFGR_PLLI2SN_MUL215_value		215
#define RCC_PLLI2SCFGR_PLLI2SN_MUL216_value		216
#define RCC_PLLI2SCFGR_PLLI2SN_MUL217_value		217
#define RCC_PLLI2SCFGR_PLLI2SN_MUL218_value		218
#define RCC_PLLI2SCFGR_PLLI2SN_MUL219_value		219
#define RCC_PLLI2SCFGR_PLLI2SN_MUL220_value		220
#define RCC_PLLI2SCFGR_PLLI2SN_MUL221_value		221
#define RCC_PLLI2SCFGR_PLLI2SN_MUL222_value		222
#define RCC_PLLI2SCFGR_PLLI2SN_MUL223_value		223
#define RCC_PLLI2SCFGR_PLLI2SN_MUL224_value		224
#define RCC_PLLI2SCFGR_PLLI2SN_MUL225_value		225
#define RCC_PLLI2SCFGR_PLLI2SN_MUL226_value		226
#define RCC_PLLI2SCFGR_PLLI2SN_MUL227_value		227
#define RCC_PLLI2SCFGR_PLLI2SN_MUL228_value		228
#define RCC_PLLI2SCFGR_PLLI2SN_MUL229_value		229
#define RCC_PLLI2SCFGR_PLLI2SN_MUL230_value		230
#define RCC_PLLI2SCFGR_PLLI2SN_MUL231_value		231
#define RCC_PLLI2SCFGR_PLLI2SN_MUL232_value		232
#define RCC_PLLI2SCFGR_PLLI2SN_MUL233_value		233
#define RCC_PLLI2SCFGR_PLLI2SN_MUL234_value		234
#define RCC_PLLI2SCFGR_PLLI2SN_MUL235_value		235
#define RCC_PLLI2SCFGR_PLLI2SN_MUL236_value		236
#define RCC_PLLI2SCFGR_PLLI2SN_MUL237_value		237
#define RCC_PLLI2SCFGR_PLLI2SN_MUL238_value		238
#define RCC_PLLI2SCFGR_PLLI2SN_MUL239_value		239
#define RCC_PLLI2SCFGR_PLLI2SN_MUL240_value		240
#define RCC_PLLI2SCFGR_PLLI2SN_MUL241_value		241
#define RCC_PLLI2SCFGR_PLLI2SN_MUL242_value		242
#define RCC_PLLI2SCFGR_PLLI2SN_MUL243_value		243
#define RCC_PLLI2SCFGR_PLLI2SN_MUL244_value		244
#define RCC_PLLI2SCFGR_PLLI2SN_MUL245_value		245
#define RCC_PLLI2SCFGR_PLLI2SN_MUL246_value		246
#define RCC_PLLI2SCFGR_PLLI2SN_MUL247_value		247
#define RCC_PLLI2SCFGR_PLLI2SN_MUL248_value		248
#define RCC_PLLI2SCFGR_PLLI2SN_MUL249_value		249
#define RCC_PLLI2SCFGR_PLLI2SN_MUL250_value		250
#define RCC_PLLI2SCFGR_PLLI2SN_MUL251_value		251
#define RCC_PLLI2SCFGR_PLLI2SN_MUL252_value		252
#define RCC_PLLI2SCFGR_PLLI2SN_MUL253_value		253
#define RCC_PLLI2SCFGR_PLLI2SN_MUL254_value		254
#define RCC_PLLI2SCFGR_PLLI2SN_MUL255_value		255
#define RCC_PLLI2SCFGR_PLLI2SN_MUL256_value		256
#define RCC_PLLI2SCFGR_PLLI2SN_MUL257_value		257
#define RCC_PLLI2SCFGR_PLLI2SN_MUL258_value		258
#define RCC_PLLI2SCFGR_PLLI2SN_MUL259_value		259
#define RCC_PLLI2SCFGR_PLLI2SN_MUL260_value		260
#define RCC_PLLI2SCFGR_PLLI2SN_MUL261_value		261
#define RCC_PLLI2SCFGR_PLLI2SN_MUL262_value		262
#define RCC_PLLI2SCFGR_PLLI2SN_MUL263_value		263
#define RCC_PLLI2SCFGR_PLLI2SN_MUL264_value		264
#define RCC_PLLI2SCFGR_PLLI2SN_MUL265_value		265
#define RCC_PLLI2SCFGR_PLLI2SN_MUL266_value		266
#define RCC_PLLI2SCFGR_PLLI2SN_MUL267_value		267
#define RCC_PLLI2SCFGR_PLLI2SN_MUL268_value		268
#define RCC_PLLI2SCFGR_PLLI2SN_MUL269_value		269
#define RCC_PLLI2SCFGR_PLLI2SN_MUL270_value		270
#define RCC_PLLI2SCFGR_PLLI2SN_MUL271_value		271
#define RCC_PLLI2SCFGR_PLLI2SN_MUL272_value		272
#define RCC_PLLI2SCFGR_PLLI2SN_MUL273_value		273
#define RCC_PLLI2SCFGR_PLLI2SN_MUL274_value		274
#define RCC_PLLI2SCFGR_PLLI2SN_MUL275_value		275
#define RCC_PLLI2SCFGR_PLLI2SN_MUL276_value		276
#define RCC_PLLI2SCFGR_PLLI2SN_MUL277_value		277
#define RCC_PLLI2SCFGR_PLLI2SN_MUL278_value		278
#define RCC_PLLI2SCFGR_PLLI2SN_MUL279_value		279
#define RCC_PLLI2SCFGR_PLLI2SN_MUL280_value		280
#define RCC_PLLI2SCFGR_PLLI2SN_MUL281_value		281
#define RCC_PLLI2SCFGR_PLLI2SN_MUL282_value		282
#define RCC_PLLI2SCFGR_PLLI2SN_MUL283_value		283
#define RCC_PLLI2SCFGR_PLLI2SN_MUL284_value		284
#define RCC_PLLI2SCFGR_PLLI2SN_MUL285_value		285
#define RCC_PLLI2SCFGR_PLLI2SN_MUL286_value		286
#define RCC_PLLI2SCFGR_PLLI2SN_MUL287_value		287
#define RCC_PLLI2SCFGR_PLLI2SN_MUL288_value		288
#define RCC_PLLI2SCFGR_PLLI2SN_MUL289_value		289
#define RCC_PLLI2SCFGR_PLLI2SN_MUL290_value		290
#define RCC_PLLI2SCFGR_PLLI2SN_MUL291_value		291
#define RCC_PLLI2SCFGR_PLLI2SN_MUL292_value		292
#define RCC_PLLI2SCFGR_PLLI2SN_MUL293_value		293
#define RCC_PLLI2SCFGR_PLLI2SN_MUL294_value		294
#define RCC_PLLI2SCFGR_PLLI2SN_MUL295_value		295
#define RCC_PLLI2SCFGR_PLLI2SN_MUL296_value		296
#define RCC_PLLI2SCFGR_PLLI2SN_MUL297_value		297
#define RCC_PLLI2SCFGR_PLLI2SN_MUL298_value		298
#define RCC_PLLI2SCFGR_PLLI2SN_MUL299_value		299
#define RCC_PLLI2SCFGR_PLLI2SN_MUL300_value		300
#define RCC_PLLI2SCFGR_PLLI2SN_MUL301_value		301
#define RCC_PLLI2SCFGR_PLLI2SN_MUL302_value		302
#define RCC_PLLI2SCFGR_PLLI2SN_MUL303_value		303
#define RCC_PLLI2SCFGR_PLLI2SN_MUL304_value		304
#define RCC_PLLI2SCFGR_PLLI2SN_MUL305_value		305
#define RCC_PLLI2SCFGR_PLLI2SN_MUL306_value		306
#define RCC_PLLI2SCFGR_PLLI2SN_MUL307_value		307
#define RCC_PLLI2SCFGR_PLLI2SN_MUL308_value		308
#define RCC_PLLI2SCFGR_PLLI2SN_MUL309_value		309
#define RCC_PLLI2SCFGR_PLLI2SN_MUL310_value		310
#define RCC_PLLI2SCFGR_PLLI2SN_MUL311_value		311
#define RCC_PLLI2SCFGR_PLLI2SN_MUL312_value		312
#define RCC_PLLI2SCFGR_PLLI2SN_MUL313_value		313
#define RCC_PLLI2SCFGR_PLLI2SN_MUL314_value		314
#define RCC_PLLI2SCFGR_PLLI2SN_MUL315_value		315
#define RCC_PLLI2SCFGR_PLLI2SN_MUL316_value		316
#define RCC_PLLI2SCFGR_PLLI2SN_MUL317_value		317
#define RCC_PLLI2SCFGR_PLLI2SN_MUL318_value		318
#define RCC_PLLI2SCFGR_PLLI2SN_MUL319_value		319
#define RCC_PLLI2SCFGR_PLLI2SN_MUL320_value		320
#define RCC_PLLI2SCFGR_PLLI2SN_MUL321_value		321
#define RCC_PLLI2SCFGR_PLLI2SN_MUL322_value		322
#define RCC_PLLI2SCFGR_PLLI2SN_MUL323_value		323
#define RCC_PLLI2SCFGR_PLLI2SN_MUL324_value		324
#define RCC_PLLI2SCFGR_PLLI2SN_MUL325_value		325
#define RCC_PLLI2SCFGR_PLLI2SN_MUL326_value		326
#define RCC_PLLI2SCFGR_PLLI2SN_MUL327_value		327
#define RCC_PLLI2SCFGR_PLLI2SN_MUL328_value		328
#define RCC_PLLI2SCFGR_PLLI2SN_MUL329_value		329
#define RCC_PLLI2SCFGR_PLLI2SN_MUL330_value		330
#define RCC_PLLI2SCFGR_PLLI2SN_MUL331_value		331
#define RCC_PLLI2SCFGR_PLLI2SN_MUL332_value		332
#define RCC_PLLI2SCFGR_PLLI2SN_MUL333_value		333
#define RCC_PLLI2SCFGR_PLLI2SN_MUL334_value		334
#define RCC_PLLI2SCFGR_PLLI2SN_MUL335_value		335
#define RCC_PLLI2SCFGR_PLLI2SN_MUL336_value		336
#define RCC_PLLI2SCFGR_PLLI2SN_MUL337_value		337
#define RCC_PLLI2SCFGR_PLLI2SN_MUL338_value		338
#define RCC_PLLI2SCFGR_PLLI2SN_MUL339_value		339
#define RCC_PLLI2SCFGR_PLLI2SN_MUL340_value		340
#define RCC_PLLI2SCFGR_PLLI2SN_MUL341_value		341
#define RCC_PLLI2SCFGR_PLLI2SN_MUL342_value		342
#define RCC_PLLI2SCFGR_PLLI2SN_MUL343_value		343
#define RCC_PLLI2SCFGR_PLLI2SN_MUL344_value		344
#define RCC_PLLI2SCFGR_PLLI2SN_MUL345_value		345
#define RCC_PLLI2SCFGR_PLLI2SN_MUL346_value		346
#define RCC_PLLI2SCFGR_PLLI2SN_MUL347_value		347
#define RCC_PLLI2SCFGR_PLLI2SN_MUL348_value		348
#define RCC_PLLI2SCFGR_PLLI2SN_MUL349_value		349
#define RCC_PLLI2SCFGR_PLLI2SN_MUL350_value		350
#define RCC_PLLI2SCFGR_PLLI2SN_MUL351_value		351
#define RCC_PLLI2SCFGR_PLLI2SN_MUL352_value		352
#define RCC_PLLI2SCFGR_PLLI2SN_MUL353_value		353
#define RCC_PLLI2SCFGR_PLLI2SN_MUL354_value		354
#define RCC_PLLI2SCFGR_PLLI2SN_MUL355_value		355
#define RCC_PLLI2SCFGR_PLLI2SN_MUL356_value		356
#define RCC_PLLI2SCFGR_PLLI2SN_MUL357_value		357
#define RCC_PLLI2SCFGR_PLLI2SN_MUL358_value		358
#define RCC_PLLI2SCFGR_PLLI2SN_MUL359_value		359
#define RCC_PLLI2SCFGR_PLLI2SN_MUL360_value		360
#define RCC_PLLI2SCFGR_PLLI2SN_MUL361_value		361
#define RCC_PLLI2SCFGR_PLLI2SN_MUL362_value		362
#define RCC_PLLI2SCFGR_PLLI2SN_MUL363_value		363
#define RCC_PLLI2SCFGR_PLLI2SN_MUL364_value		364
#define RCC_PLLI2SCFGR_PLLI2SN_MUL365_value		365
#define RCC_PLLI2SCFGR_PLLI2SN_MUL366_value		366
#define RCC_PLLI2SCFGR_PLLI2SN_MUL367_value		367
#define RCC_PLLI2SCFGR_PLLI2SN_MUL368_value		368
#define RCC_PLLI2SCFGR_PLLI2SN_MUL369_value		369
#define RCC_PLLI2SCFGR_PLLI2SN_MUL370_value		370
#define RCC_PLLI2SCFGR_PLLI2SN_MUL371_value		371
#define RCC_PLLI2SCFGR_PLLI2SN_MUL372_value		372
#define RCC_PLLI2SCFGR_PLLI2SN_MUL373_value		373
#define RCC_PLLI2SCFGR_PLLI2SN_MUL374_value		374
#define RCC_PLLI2SCFGR_PLLI2SN_MUL375_value		375
#define RCC_PLLI2SCFGR_PLLI2SN_MUL376_value		376
#define RCC_PLLI2SCFGR_PLLI2SN_MUL377_value		377
#define RCC_PLLI2SCFGR_PLLI2SN_MUL378_value		378
#define RCC_PLLI2SCFGR_PLLI2SN_MUL379_value		379
#define RCC_PLLI2SCFGR_PLLI2SN_MUL380_value		380
#define RCC_PLLI2SCFGR_PLLI2SN_MUL381_value		381
#define RCC_PLLI2SCFGR_PLLI2SN_MUL382_value		382
#define RCC_PLLI2SCFGR_PLLI2SN_MUL383_value		383
#define RCC_PLLI2SCFGR_PLLI2SN_MUL384_value		384
#define RCC_PLLI2SCFGR_PLLI2SN_MUL385_value		385
#define RCC_PLLI2SCFGR_PLLI2SN_MUL386_value		386
#define RCC_PLLI2SCFGR_PLLI2SN_MUL387_value		387
#define RCC_PLLI2SCFGR_PLLI2SN_MUL388_value		388
#define RCC_PLLI2SCFGR_PLLI2SN_MUL389_value		389
#define RCC_PLLI2SCFGR_PLLI2SN_MUL390_value		390
#define RCC_PLLI2SCFGR_PLLI2SN_MUL391_value		391
#define RCC_PLLI2SCFGR_PLLI2SN_MUL392_value		392
#define RCC_PLLI2SCFGR_PLLI2SN_MUL393_value		393
#define RCC_PLLI2SCFGR_PLLI2SN_MUL394_value		394
#define RCC_PLLI2SCFGR_PLLI2SN_MUL395_value		395
#define RCC_PLLI2SCFGR_PLLI2SN_MUL396_value		396
#define RCC_PLLI2SCFGR_PLLI2SN_MUL397_value		397
#define RCC_PLLI2SCFGR_PLLI2SN_MUL398_value		398
#define RCC_PLLI2SCFGR_PLLI2SN_MUL399_value		399
#define RCC_PLLI2SCFGR_PLLI2SN_MUL400_value		400
#define RCC_PLLI2SCFGR_PLLI2SN_MUL401_value		401
#define RCC_PLLI2SCFGR_PLLI2SN_MUL402_value		402
#define RCC_PLLI2SCFGR_PLLI2SN_MUL403_value		403
#define RCC_PLLI2SCFGR_PLLI2SN_MUL404_value		404
#define RCC_PLLI2SCFGR_PLLI2SN_MUL405_value		405
#define RCC_PLLI2SCFGR_PLLI2SN_MUL406_value		406
#define RCC_PLLI2SCFGR_PLLI2SN_MUL407_value		407
#define RCC_PLLI2SCFGR_PLLI2SN_MUL408_value		408
#define RCC_PLLI2SCFGR_PLLI2SN_MUL409_value		409
#define RCC_PLLI2SCFGR_PLLI2SN_MUL410_value		410
#define RCC_PLLI2SCFGR_PLLI2SN_MUL411_value		411
#define RCC_PLLI2SCFGR_PLLI2SN_MUL412_value		412
#define RCC_PLLI2SCFGR_PLLI2SN_MUL413_value		413
#define RCC_PLLI2SCFGR_PLLI2SN_MUL414_value		414
#define RCC_PLLI2SCFGR_PLLI2SN_MUL415_value		415
#define RCC_PLLI2SCFGR_PLLI2SN_MUL416_value		416
#define RCC_PLLI2SCFGR_PLLI2SN_MUL417_value		417
#define RCC_PLLI2SCFGR_PLLI2SN_MUL418_value		418
#define RCC_PLLI2SCFGR_PLLI2SN_MUL419_value		419
#define RCC_PLLI2SCFGR_PLLI2SN_MUL420_value		420
#define RCC_PLLI2SCFGR_PLLI2SN_MUL421_value		421
#define RCC_PLLI2SCFGR_PLLI2SN_MUL422_value		422
#define RCC_PLLI2SCFGR_PLLI2SN_MUL423_value		423
#define RCC_PLLI2SCFGR_PLLI2SN_MUL424_value		424
#define RCC_PLLI2SCFGR_PLLI2SN_MUL425_value		425
#define RCC_PLLI2SCFGR_PLLI2SN_MUL426_value		426
#define RCC_PLLI2SCFGR_PLLI2SN_MUL427_value		427
#define RCC_PLLI2SCFGR_PLLI2SN_MUL428_value		428
#define RCC_PLLI2SCFGR_PLLI2SN_MUL429_value		429
#define RCC_PLLI2SCFGR_PLLI2SN_MUL430_value		430
#define RCC_PLLI2SCFGR_PLLI2SN_MUL431_value		431
#define RCC_PLLI2SCFGR_PLLI2SN_MUL432_value		432
#define RCC_PLLI2SCFGR_PLLI2SN_mask				511

#define RCC_PLLI2SCFGR_PLLI2SR_DIV2			(RCC_PLLI2SCFGR_PLLI2SR_DIV2_value << RCC_PLLI2SCFGR_PLLI2SR_bit)
#define RCC_PLLI2SCFGR_PLLI2SR_DIV3			(RCC_PLLI2SCFGR_PLLI2SR_DIV3_value << RCC_PLLI2SCFGR_PLLI2SR_bit)
#define RCC_PLLI2SCFGR_PLLI2SR_DIV4			(RCC_PLLI2SCFGR_PLLI2SR_DIV4_value << RCC_PLLI2SCFGR_PLLI2SR_bit)
#define RCC_PLLI2SCFGR_PLLI2SR_DIV5			(RCC_PLLI2SCFGR_PLLI2SR_DIV5_value << RCC_PLLI2SCFGR_PLLI2SR_bit)
#define RCC_PLLI2SCFGR_PLLI2SR_DIV6			(RCC_PLLI2SCFGR_PLLI2SR_DIV6_value << RCC_PLLI2SCFGR_PLLI2SR_bit)
#define RCC_PLLI2SCFGR_PLLI2SR_DIV7			(RCC_PLLI2SCFGR_PLLI2SR_DIV7_value << RCC_PLLI2SCFGR_PLLI2SR_bit)

#define RCC_PLLI2SCFGR_PLLI2SN_MUL192		(RCC_PLLI2SCFGR_PLLI2SN_MUL192_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL193		(RCC_PLLI2SCFGR_PLLI2SN_MUL193_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL194		(RCC_PLLI2SCFGR_PLLI2SN_MUL194_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL195		(RCC_PLLI2SCFGR_PLLI2SN_MUL195_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL196		(RCC_PLLI2SCFGR_PLLI2SN_MUL196_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL197		(RCC_PLLI2SCFGR_PLLI2SN_MUL197_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL198		(RCC_PLLI2SCFGR_PLLI2SN_MUL198_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL199		(RCC_PLLI2SCFGR_PLLI2SN_MUL199_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL200		(RCC_PLLI2SCFGR_PLLI2SN_MUL200_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL201		(RCC_PLLI2SCFGR_PLLI2SN_MUL201_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL202		(RCC_PLLI2SCFGR_PLLI2SN_MUL202_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL203		(RCC_PLLI2SCFGR_PLLI2SN_MUL203_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL204		(RCC_PLLI2SCFGR_PLLI2SN_MUL204_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL205		(RCC_PLLI2SCFGR_PLLI2SN_MUL205_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL206		(RCC_PLLI2SCFGR_PLLI2SN_MUL206_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL207		(RCC_PLLI2SCFGR_PLLI2SN_MUL207_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL208		(RCC_PLLI2SCFGR_PLLI2SN_MUL208_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL209		(RCC_PLLI2SCFGR_PLLI2SN_MUL209_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL210		(RCC_PLLI2SCFGR_PLLI2SN_MUL210_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL211		(RCC_PLLI2SCFGR_PLLI2SN_MUL211_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL212		(RCC_PLLI2SCFGR_PLLI2SN_MUL212_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL213		(RCC_PLLI2SCFGR_PLLI2SN_MUL213_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL214		(RCC_PLLI2SCFGR_PLLI2SN_MUL214_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL215		(RCC_PLLI2SCFGR_PLLI2SN_MUL215_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL216		(RCC_PLLI2SCFGR_PLLI2SN_MUL216_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL217		(RCC_PLLI2SCFGR_PLLI2SN_MUL217_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL218		(RCC_PLLI2SCFGR_PLLI2SN_MUL218_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL219		(RCC_PLLI2SCFGR_PLLI2SN_MUL219_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL220		(RCC_PLLI2SCFGR_PLLI2SN_MUL220_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL221		(RCC_PLLI2SCFGR_PLLI2SN_MUL221_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL222		(RCC_PLLI2SCFGR_PLLI2SN_MUL222_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL223		(RCC_PLLI2SCFGR_PLLI2SN_MUL223_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL224		(RCC_PLLI2SCFGR_PLLI2SN_MUL224_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL225		(RCC_PLLI2SCFGR_PLLI2SN_MUL225_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL226		(RCC_PLLI2SCFGR_PLLI2SN_MUL226_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL227		(RCC_PLLI2SCFGR_PLLI2SN_MUL227_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL228		(RCC_PLLI2SCFGR_PLLI2SN_MUL228_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL229		(RCC_PLLI2SCFGR_PLLI2SN_MUL229_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL230		(RCC_PLLI2SCFGR_PLLI2SN_MUL230_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL231		(RCC_PLLI2SCFGR_PLLI2SN_MUL231_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL232		(RCC_PLLI2SCFGR_PLLI2SN_MUL232_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL233		(RCC_PLLI2SCFGR_PLLI2SN_MUL233_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL234		(RCC_PLLI2SCFGR_PLLI2SN_MUL234_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL235		(RCC_PLLI2SCFGR_PLLI2SN_MUL235_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL236		(RCC_PLLI2SCFGR_PLLI2SN_MUL236_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL237		(RCC_PLLI2SCFGR_PLLI2SN_MUL237_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL238		(RCC_PLLI2SCFGR_PLLI2SN_MUL238_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL239		(RCC_PLLI2SCFGR_PLLI2SN_MUL239_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL240		(RCC_PLLI2SCFGR_PLLI2SN_MUL240_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL241		(RCC_PLLI2SCFGR_PLLI2SN_MUL241_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL242		(RCC_PLLI2SCFGR_PLLI2SN_MUL242_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL243		(RCC_PLLI2SCFGR_PLLI2SN_MUL243_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL244		(RCC_PLLI2SCFGR_PLLI2SN_MUL244_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL245		(RCC_PLLI2SCFGR_PLLI2SN_MUL245_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL246		(RCC_PLLI2SCFGR_PLLI2SN_MUL246_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL247		(RCC_PLLI2SCFGR_PLLI2SN_MUL247_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL248		(RCC_PLLI2SCFGR_PLLI2SN_MUL248_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL249		(RCC_PLLI2SCFGR_PLLI2SN_MUL249_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL250		(RCC_PLLI2SCFGR_PLLI2SN_MUL250_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL251		(RCC_PLLI2SCFGR_PLLI2SN_MUL251_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL252		(RCC_PLLI2SCFGR_PLLI2SN_MUL252_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL253		(RCC_PLLI2SCFGR_PLLI2SN_MUL253_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL254		(RCC_PLLI2SCFGR_PLLI2SN_MUL254_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL255		(RCC_PLLI2SCFGR_PLLI2SN_MUL255_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL256		(RCC_PLLI2SCFGR_PLLI2SN_MUL256_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL257		(RCC_PLLI2SCFGR_PLLI2SN_MUL257_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL258		(RCC_PLLI2SCFGR_PLLI2SN_MUL258_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL259		(RCC_PLLI2SCFGR_PLLI2SN_MUL259_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL260		(RCC_PLLI2SCFGR_PLLI2SN_MUL260_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL261		(RCC_PLLI2SCFGR_PLLI2SN_MUL261_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL262		(RCC_PLLI2SCFGR_PLLI2SN_MUL262_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL263		(RCC_PLLI2SCFGR_PLLI2SN_MUL263_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL264		(RCC_PLLI2SCFGR_PLLI2SN_MUL264_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL265		(RCC_PLLI2SCFGR_PLLI2SN_MUL265_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL266		(RCC_PLLI2SCFGR_PLLI2SN_MUL266_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL267		(RCC_PLLI2SCFGR_PLLI2SN_MUL267_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL268		(RCC_PLLI2SCFGR_PLLI2SN_MUL268_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL269		(RCC_PLLI2SCFGR_PLLI2SN_MUL269_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL270		(RCC_PLLI2SCFGR_PLLI2SN_MUL270_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL271		(RCC_PLLI2SCFGR_PLLI2SN_MUL271_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL272		(RCC_PLLI2SCFGR_PLLI2SN_MUL272_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL273		(RCC_PLLI2SCFGR_PLLI2SN_MUL273_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL274		(RCC_PLLI2SCFGR_PLLI2SN_MUL274_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL275		(RCC_PLLI2SCFGR_PLLI2SN_MUL275_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL276		(RCC_PLLI2SCFGR_PLLI2SN_MUL276_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL277		(RCC_PLLI2SCFGR_PLLI2SN_MUL277_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL278		(RCC_PLLI2SCFGR_PLLI2SN_MUL278_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL279		(RCC_PLLI2SCFGR_PLLI2SN_MUL279_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL280		(RCC_PLLI2SCFGR_PLLI2SN_MUL280_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL281		(RCC_PLLI2SCFGR_PLLI2SN_MUL281_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL282		(RCC_PLLI2SCFGR_PLLI2SN_MUL282_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL283		(RCC_PLLI2SCFGR_PLLI2SN_MUL283_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL284		(RCC_PLLI2SCFGR_PLLI2SN_MUL284_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL285		(RCC_PLLI2SCFGR_PLLI2SN_MUL285_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL286		(RCC_PLLI2SCFGR_PLLI2SN_MUL286_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL287		(RCC_PLLI2SCFGR_PLLI2SN_MUL287_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL288		(RCC_PLLI2SCFGR_PLLI2SN_MUL288_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL289		(RCC_PLLI2SCFGR_PLLI2SN_MUL289_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL290		(RCC_PLLI2SCFGR_PLLI2SN_MUL290_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL291		(RCC_PLLI2SCFGR_PLLI2SN_MUL291_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL292		(RCC_PLLI2SCFGR_PLLI2SN_MUL292_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL293		(RCC_PLLI2SCFGR_PLLI2SN_MUL293_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL294		(RCC_PLLI2SCFGR_PLLI2SN_MUL294_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL295		(RCC_PLLI2SCFGR_PLLI2SN_MUL295_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL296		(RCC_PLLI2SCFGR_PLLI2SN_MUL296_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL297		(RCC_PLLI2SCFGR_PLLI2SN_MUL297_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL298		(RCC_PLLI2SCFGR_PLLI2SN_MUL298_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL299		(RCC_PLLI2SCFGR_PLLI2SN_MUL299_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL300		(RCC_PLLI2SCFGR_PLLI2SN_MUL300_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL301		(RCC_PLLI2SCFGR_PLLI2SN_MUL301_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL302		(RCC_PLLI2SCFGR_PLLI2SN_MUL302_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL303		(RCC_PLLI2SCFGR_PLLI2SN_MUL303_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL304		(RCC_PLLI2SCFGR_PLLI2SN_MUL304_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL305		(RCC_PLLI2SCFGR_PLLI2SN_MUL305_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL306		(RCC_PLLI2SCFGR_PLLI2SN_MUL306_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL307		(RCC_PLLI2SCFGR_PLLI2SN_MUL307_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL308		(RCC_PLLI2SCFGR_PLLI2SN_MUL308_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL309		(RCC_PLLI2SCFGR_PLLI2SN_MUL309_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL310		(RCC_PLLI2SCFGR_PLLI2SN_MUL310_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL311		(RCC_PLLI2SCFGR_PLLI2SN_MUL311_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL312		(RCC_PLLI2SCFGR_PLLI2SN_MUL312_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL313		(RCC_PLLI2SCFGR_PLLI2SN_MUL313_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL314		(RCC_PLLI2SCFGR_PLLI2SN_MUL314_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL315		(RCC_PLLI2SCFGR_PLLI2SN_MUL315_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL316		(RCC_PLLI2SCFGR_PLLI2SN_MUL316_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL317		(RCC_PLLI2SCFGR_PLLI2SN_MUL317_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL318		(RCC_PLLI2SCFGR_PLLI2SN_MUL318_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL319		(RCC_PLLI2SCFGR_PLLI2SN_MUL319_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL320		(RCC_PLLI2SCFGR_PLLI2SN_MUL320_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL321		(RCC_PLLI2SCFGR_PLLI2SN_MUL321_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL322		(RCC_PLLI2SCFGR_PLLI2SN_MUL322_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL323		(RCC_PLLI2SCFGR_PLLI2SN_MUL323_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL324		(RCC_PLLI2SCFGR_PLLI2SN_MUL324_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL325		(RCC_PLLI2SCFGR_PLLI2SN_MUL325_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL326		(RCC_PLLI2SCFGR_PLLI2SN_MUL326_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL327		(RCC_PLLI2SCFGR_PLLI2SN_MUL327_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL328		(RCC_PLLI2SCFGR_PLLI2SN_MUL328_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL329		(RCC_PLLI2SCFGR_PLLI2SN_MUL329_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL330		(RCC_PLLI2SCFGR_PLLI2SN_MUL330_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL331		(RCC_PLLI2SCFGR_PLLI2SN_MUL331_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL332		(RCC_PLLI2SCFGR_PLLI2SN_MUL332_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL333		(RCC_PLLI2SCFGR_PLLI2SN_MUL333_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL334		(RCC_PLLI2SCFGR_PLLI2SN_MUL334_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL335		(RCC_PLLI2SCFGR_PLLI2SN_MUL335_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL336		(RCC_PLLI2SCFGR_PLLI2SN_MUL336_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL337		(RCC_PLLI2SCFGR_PLLI2SN_MUL337_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL338		(RCC_PLLI2SCFGR_PLLI2SN_MUL338_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL339		(RCC_PLLI2SCFGR_PLLI2SN_MUL339_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL340		(RCC_PLLI2SCFGR_PLLI2SN_MUL340_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL341		(RCC_PLLI2SCFGR_PLLI2SN_MUL341_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL342		(RCC_PLLI2SCFGR_PLLI2SN_MUL342_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL343		(RCC_PLLI2SCFGR_PLLI2SN_MUL343_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL344		(RCC_PLLI2SCFGR_PLLI2SN_MUL344_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL345		(RCC_PLLI2SCFGR_PLLI2SN_MUL345_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL346		(RCC_PLLI2SCFGR_PLLI2SN_MUL346_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL347		(RCC_PLLI2SCFGR_PLLI2SN_MUL347_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL348		(RCC_PLLI2SCFGR_PLLI2SN_MUL348_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL349		(RCC_PLLI2SCFGR_PLLI2SN_MUL349_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL350		(RCC_PLLI2SCFGR_PLLI2SN_MUL350_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL351		(RCC_PLLI2SCFGR_PLLI2SN_MUL351_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL352		(RCC_PLLI2SCFGR_PLLI2SN_MUL352_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL353		(RCC_PLLI2SCFGR_PLLI2SN_MUL353_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL354		(RCC_PLLI2SCFGR_PLLI2SN_MUL354_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL355		(RCC_PLLI2SCFGR_PLLI2SN_MUL355_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL356		(RCC_PLLI2SCFGR_PLLI2SN_MUL356_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL357		(RCC_PLLI2SCFGR_PLLI2SN_MUL357_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL358		(RCC_PLLI2SCFGR_PLLI2SN_MUL358_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL359		(RCC_PLLI2SCFGR_PLLI2SN_MUL359_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL360		(RCC_PLLI2SCFGR_PLLI2SN_MUL360_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL361		(RCC_PLLI2SCFGR_PLLI2SN_MUL361_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL362		(RCC_PLLI2SCFGR_PLLI2SN_MUL362_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL363		(RCC_PLLI2SCFGR_PLLI2SN_MUL363_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL364		(RCC_PLLI2SCFGR_PLLI2SN_MUL364_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL365		(RCC_PLLI2SCFGR_PLLI2SN_MUL365_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL366		(RCC_PLLI2SCFGR_PLLI2SN_MUL366_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL367		(RCC_PLLI2SCFGR_PLLI2SN_MUL367_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL368		(RCC_PLLI2SCFGR_PLLI2SN_MUL368_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL369		(RCC_PLLI2SCFGR_PLLI2SN_MUL369_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL370		(RCC_PLLI2SCFGR_PLLI2SN_MUL370_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL371		(RCC_PLLI2SCFGR_PLLI2SN_MUL371_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL372		(RCC_PLLI2SCFGR_PLLI2SN_MUL372_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL373		(RCC_PLLI2SCFGR_PLLI2SN_MUL373_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL374		(RCC_PLLI2SCFGR_PLLI2SN_MUL374_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL375		(RCC_PLLI2SCFGR_PLLI2SN_MUL375_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL376		(RCC_PLLI2SCFGR_PLLI2SN_MUL376_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL377		(RCC_PLLI2SCFGR_PLLI2SN_MUL377_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL378		(RCC_PLLI2SCFGR_PLLI2SN_MUL378_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL379		(RCC_PLLI2SCFGR_PLLI2SN_MUL379_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL380		(RCC_PLLI2SCFGR_PLLI2SN_MUL380_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL381		(RCC_PLLI2SCFGR_PLLI2SN_MUL381_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL382		(RCC_PLLI2SCFGR_PLLI2SN_MUL382_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL383		(RCC_PLLI2SCFGR_PLLI2SN_MUL383_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL384		(RCC_PLLI2SCFGR_PLLI2SN_MUL384_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL385		(RCC_PLLI2SCFGR_PLLI2SN_MUL385_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL386		(RCC_PLLI2SCFGR_PLLI2SN_MUL386_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL387		(RCC_PLLI2SCFGR_PLLI2SN_MUL387_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL388		(RCC_PLLI2SCFGR_PLLI2SN_MUL388_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL389		(RCC_PLLI2SCFGR_PLLI2SN_MUL389_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL390		(RCC_PLLI2SCFGR_PLLI2SN_MUL390_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL391		(RCC_PLLI2SCFGR_PLLI2SN_MUL391_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL392		(RCC_PLLI2SCFGR_PLLI2SN_MUL392_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL393		(RCC_PLLI2SCFGR_PLLI2SN_MUL393_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL394		(RCC_PLLI2SCFGR_PLLI2SN_MUL394_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL395		(RCC_PLLI2SCFGR_PLLI2SN_MUL395_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL396		(RCC_PLLI2SCFGR_PLLI2SN_MUL396_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL397		(RCC_PLLI2SCFGR_PLLI2SN_MUL397_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL398		(RCC_PLLI2SCFGR_PLLI2SN_MUL398_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL399		(RCC_PLLI2SCFGR_PLLI2SN_MUL399_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL400		(RCC_PLLI2SCFGR_PLLI2SN_MUL400_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL401		(RCC_PLLI2SCFGR_PLLI2SN_MUL401_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL402		(RCC_PLLI2SCFGR_PLLI2SN_MUL402_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL403		(RCC_PLLI2SCFGR_PLLI2SN_MUL403_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL404		(RCC_PLLI2SCFGR_PLLI2SN_MUL404_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL405		(RCC_PLLI2SCFGR_PLLI2SN_MUL405_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL406		(RCC_PLLI2SCFGR_PLLI2SN_MUL406_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL407		(RCC_PLLI2SCFGR_PLLI2SN_MUL407_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL408		(RCC_PLLI2SCFGR_PLLI2SN_MUL408_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL409		(RCC_PLLI2SCFGR_PLLI2SN_MUL409_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL410		(RCC_PLLI2SCFGR_PLLI2SN_MUL410_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL411		(RCC_PLLI2SCFGR_PLLI2SN_MUL411_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL412		(RCC_PLLI2SCFGR_PLLI2SN_MUL412_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL413		(RCC_PLLI2SCFGR_PLLI2SN_MUL413_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL414		(RCC_PLLI2SCFGR_PLLI2SN_MUL414_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL415		(RCC_PLLI2SCFGR_PLLI2SN_MUL415_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL416		(RCC_PLLI2SCFGR_PLLI2SN_MUL416_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL417		(RCC_PLLI2SCFGR_PLLI2SN_MUL417_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL418		(RCC_PLLI2SCFGR_PLLI2SN_MUL418_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL419		(RCC_PLLI2SCFGR_PLLI2SN_MUL419_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL420		(RCC_PLLI2SCFGR_PLLI2SN_MUL420_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL421		(RCC_PLLI2SCFGR_PLLI2SN_MUL421_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL422		(RCC_PLLI2SCFGR_PLLI2SN_MUL422_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL423		(RCC_PLLI2SCFGR_PLLI2SN_MUL423_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL424		(RCC_PLLI2SCFGR_PLLI2SN_MUL424_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL425		(RCC_PLLI2SCFGR_PLLI2SN_MUL425_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL426		(RCC_PLLI2SCFGR_PLLI2SN_MUL426_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL427		(RCC_PLLI2SCFGR_PLLI2SN_MUL427_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL428		(RCC_PLLI2SCFGR_PLLI2SN_MUL428_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL429		(RCC_PLLI2SCFGR_PLLI2SN_MUL429_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL430		(RCC_PLLI2SCFGR_PLLI2SN_MUL430_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL431		(RCC_PLLI2SCFGR_PLLI2SN_MUL431_value << RCC_PLLI2SCFGR_PLLI2SN_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_MUL432		(RCC_PLLI2SCFGR_PLLI2SN_MUL432_value << RCC_PLLI2SCFGR_PLLI2SN_bit)

#define RCC_PLLI2SCFGR_PLLI2SR_0_bb			bitband_t m_BITBAND_PERIPH(&RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR_0_bit)
#define RCC_PLLI2SCFGR_PLLI2SR_1_bb			bitband_t m_BITBAND_PERIPH(&RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR_1_bit)
#define RCC_PLLI2SCFGR_PLLI2SR_2_bb			bitband_t m_BITBAND_PERIPH(&RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR_2_bit)

#define RCC_PLLI2SCFGR_PLLI2SN_0_bb			bitband_t m_BITBAND_PERIPH(&RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_0_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_1_bb			bitband_t m_BITBAND_PERIPH(&RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_1_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_2_bb			bitband_t m_BITBAND_PERIPH(&RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_2_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_3_bb			bitband_t m_BITBAND_PERIPH(&RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_3_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_4_bb			bitband_t m_BITBAND_PERIPH(&RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_4_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_5_bb			bitband_t m_BITBAND_PERIPH(&RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_5_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_6_bb			bitband_t m_BITBAND_PERIPH(&RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_7_bb			bitband_t m_BITBAND_PERIPH(&RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_7_bit)
#define RCC_PLLI2SCFGR_PLLI2SN_8_bb			bitband_t m_BITBAND_PERIPH(&RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_8_bit)

/******************************************************************************
* END OF FILE
******************************************************************************/
#endif /* HDR_RCC_H_ */
